Searched refs:faddv (Results 1 – 25 of 25) sorted by relevance
3 faddv b0, p7, z31.b label12 faddv h0, p8, z31.h label17 faddv h0, p7.b, z31.h label22 faddv h0, p7.q, z31.h label31 faddv v0, p7, z31.h label40 faddv d0, p7, z31.d define46 faddv d0, p7, z31.d define
10 faddv h0, p7, z31.h label16 faddv s0, p7, z31.s label22 faddv d0, p7, z31.d define
16 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #221 ; CHECK-NEXT: faddv d2, p0, z0.d22 ; CHECK-NEXT: faddv d0, p0, z1.d29 …%3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %2)31 …%5 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %4)
47 ; CHECK: faddv h0, p0, z0.h49 %res = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %pg,56 ; CHECK: faddv s0, p0, z0.s58 %res = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %pg,65 ; CHECK: faddv d0, p0, z0.d67 %res = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pg,200 declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)201 declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)202 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
254 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h265 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], z1.h276 ; CHECK-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h288 ; VBITS_GE_512-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h298 ; VBITS_EQ_256-DAG: faddv h1, [[PG]], [[ADD]].h310 ; VBITS_GE_1024-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h322 ; VBITS_GE_2048-NEXT: faddv [[RDX:h[0-9]+]], [[PG]], [[OP]].h344 ; CHECK-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], z1.s355 ; CHECK-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s367 ; VBITS_GE_512-NEXT: faddv [[RDX:s[0-9]+]], [[PG]], [[OP]].s[all …]
187 %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)197 %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)206 %vaddv.i = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)405 declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)406 declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)407 declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
445 ; CHECK-NEXT: faddv d0, p0, z0.d446 ; CHECK-NEXT: faddv d1, p0, z1.d452 …%1 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %i…453 …%2 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pred, <vscale x 2 x double> %i…832 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
199 declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
1426 COMPARE_PREFIX(faddv(h26, p6, z16.VnH()), "faddv h26, p6, z16.h"); in TEST()1427 COMPARE_PREFIX(faddv(s26, p6, z16.VnS()), "faddv s26, p6, z16.s"); in TEST()1428 COMPARE_PREFIX(faddv(d26, p6, z16.VnD()), "faddv d26, p6, z16.d"); in TEST()
4292 LogicVRegister faddv(VectorFormat vform,
4084 void faddv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
1345 void Assembler::faddv(const VRegister& vd, in faddv() function in vixl::aarch64::Assembler
5428 LogicVRegister Simulator::faddv(VectorFormat vform, in faddv() function in vixl::aarch64::Simulator
4178 faddv(vd, pg, zn); in Faddv()
8189 fn = &Simulator::faddv; in VisitSVEFPFastReduction()
239 defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv", int_aarch64_sve_faddv>;
12497 "\005fadda\005faddp\005faddv\005fcadd\005fccmp\006fccmpe\005fcmeq\005fcm"13696 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…13697 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…13698 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…21069 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…21070 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…21071 …{ 1089 /* faddv */, AArch64::FADDV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…29639 { 1089 /* faddv */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },29640 { 1089 /* faddv */, 4 /* 2 */, MCK_SVEVectorHReg, AMFBS_HasSVE },29641 { 1089 /* faddv */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },[all …]
493 defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv", AArch64faddv_p>;
353 "llvm.aarch64.neon.faddv",570 "llvm.aarch64.sve.faddv",10486 1, // llvm.aarch64.neon.faddv10703 1, // llvm.aarch64.sve.faddv
200 aarch64_neon_faddv, // llvm.aarch64.neon.faddv6258 "llvm.aarch64.neon.faddv",14198 1, // llvm.aarch64.neon.faddv
192 aarch64_neon_faddv, // llvm.aarch64.neon.faddv6216 "llvm.aarch64.neon.faddv",14101 1, // llvm.aarch64.neon.faddv