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Searched refs:fbits (Results 1 – 25 of 30) sorted by relevance

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/external/cbor-java/src/main/java/co/nstant/in/cbor/encoder/
DHalfPrecisionFloatEncoder.java29 int fbits = Float.floatToIntBits(fval); in fromFloat() local
30 int sign = fbits >>> 16 & 0x8000; // sign only in fromFloat()
31 int val = 0x1000 + fbits & 0x7fffffff; // rounded value in fromFloat()
35 if ((fbits & 0x7fffffff) >= 0x47800000) { // is or must become in fromFloat()
41 (fbits & 0x007fffff) >>> 13; // keep NaN (and in fromFloat()
52 val = (fbits & 0x7fffffff) >>> 23; // tmp exp for subnormal calc in fromFloat()
53 return sign | ((fbits & 0x7fffff | 0x800000) // add subnormal bit in fromFloat()
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc4419 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtfHelper() local
4420 __ Scvtf(d0, x10, fbits); in TestUScvtfHelper()
4421 __ Ucvtf(d1, x10, fbits); in TestUScvtfHelper()
4422 __ Scvtf(d2, w11, fbits); in TestUScvtfHelper()
4423 __ Ucvtf(d3, w11, fbits); in TestUScvtfHelper()
4424 __ Str(d0, MemOperand(x0, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
4425 __ Str(d1, MemOperand(x1, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
4426 __ Str(d2, MemOperand(x2, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
4427 __ Str(d3, MemOperand(x3, fbits * kDRegSizeInBytes)); in TestUScvtfHelper()
4432 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
[all …]
Dtest-simulator-aarch64.cc194 int fbits);
197 int fbits);
1014 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper() local
1017 (masm.*helper)(rd, fn, fbits); in TestFPToFixed_Helper()
1323 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS() local
1331 fbits, in TestFPToFixedS()
1334 fbits); in TestFPToFixedS()
1401 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedU() local
1409 fbits, in TestFPToFixedU()
1412 fbits); in TestFPToFixedU()
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td78 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
80 // source. It's encoded as "Size - fbits" where Size is the size of the
81 // fixed-point representation (32 or 16) and fbits is the value appearing
1554 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1555 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1559 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1560 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1564 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1565 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1569 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td121 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
123 // source. It's encoded as "Size - fbits" where Size is the size of the
124 // fixed-point representation (32 or 16) and fbits is the value appearing
1701 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1702 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1707 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1708 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1713 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1714 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1719 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td131 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
133 // source. It's encoded as "Size - fbits" where Size is the size of the
134 // fixed-point representation (32 or 16) and fbits is the value appearing
1786 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1787 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1792 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1793 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1798 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1799 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1804 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
[all …]
/external/python/cpython3/Objects/
Dfloatobject.c2131 unsigned int fbits; in _PyFloat_Pack4() local
2174 fbits = (unsigned int)(f + 0.5); /* Round */ in _PyFloat_Pack4()
2175 assert(fbits <= 8388608); in _PyFloat_Pack4()
2176 if (fbits >> 23) { in _PyFloat_Pack4()
2178 fbits = 0; in _PyFloat_Pack4()
2189 *p = (char) (((e & 1) << 7) | (fbits >> 16)); in _PyFloat_Pack4()
2193 *p = (fbits >> 8) & 0xFF; in _PyFloat_Pack4()
2197 *p = fbits & 0xFF; in _PyFloat_Pack4()
/external/python/cpython2/Objects/
Dfloatobject.c2318 unsigned int fbits; in _PyFloat_Pack4() local
2361 fbits = (unsigned int)(f + 0.5); /* Round */ in _PyFloat_Pack4()
2362 assert(fbits <= 8388608); in _PyFloat_Pack4()
2363 if (fbits >> 23) { in _PyFloat_Pack4()
2365 fbits = 0; in _PyFloat_Pack4()
2376 *p = (char) (((e & 1) << 7) | (fbits >> 16)); in _PyFloat_Pack4()
2380 *p = (fbits >> 8) & 0xFF; in _PyFloat_Pack4()
2384 *p = fbits & 0xFF; in _PyFloat_Pack4()
/external/vixl/src/aarch64/
Dlogic-aarch64.cc87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble() argument
89 return UFixedToDouble(src, fbits, round); in FixedToDouble()
91 return -UFixedToDouble(src, fbits, round); in FixedToDouble()
93 return -UFixedToDouble(-src, fbits, round); in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble() argument
108 const int64_t exponent = highest_significant_bit - fbits; in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat() argument
116 return UFixedToFloat(src, fbits, round); in FixedToFloat()
118 return -UFixedToFloat(src, fbits, round); in FixedToFloat()
120 return -UFixedToFloat(-src, fbits, round); in FixedToFloat()
[all …]
Dassembler-aarch64.cc3164 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in NEON_FP2REGMISC_FCVT_LIST()
3168 VIXL_ASSERT((fbits >= 0) && (fbits <= rd.GetSizeInBits())); in NEON_FP2REGMISC_FCVT_LIST()
3169 if (fbits == 0) { in NEON_FP2REGMISC_FCVT_LIST()
3172 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) | in NEON_FP2REGMISC_FCVT_LIST()
3178 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs() argument
3182 VIXL_ASSERT(fbits >= 0); in fcvtzs()
3183 if (fbits == 0) { in fcvtzs()
3192 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm); in fcvtzs()
3197 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu() argument
3201 VIXL_ASSERT((fbits >= 0) && (fbits <= rd.GetSizeInBits())); in fcvtzu()
[all …]
Dsimulator-aarch64.h3678 int fbits = 0);
3682 int fbits,
3691 int fbits = 0);
3695 int fbits,
4153 int fbits = 0);
4158 int fbits = 0);
4166 int fbits = 0);
4171 int fbits = 0);
4310 R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding);
4320 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
[all …]
Dsimulator-aarch64.cc3833 int fbits = 64 - instr->GetFPScale(); in VisitFPFixedPointConvert() local
3841 WriteDRegister(dst, FixedToDouble(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3844 WriteDRegister(dst, FixedToDouble(ReadWRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3847 WriteDRegister(dst, UFixedToDouble(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3851 UFixedToDouble(ReadRegister<uint32_t>(src), fbits, round)); in VisitFPFixedPointConvert()
3855 WriteSRegister(dst, FixedToFloat(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3858 WriteSRegister(dst, FixedToFloat(ReadWRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3861 WriteSRegister(dst, UFixedToFloat(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
3865 UFixedToFloat(ReadRegister<uint32_t>(src), fbits, round)); in VisitFPFixedPointConvert()
3869 WriteHRegister(dst, FixedToFloat16(ReadXRegister(src), fbits, round)); in VisitFPFixedPointConvert()
[all …]
Dmacro-assembler-aarch64.h1534 void Fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) {
1538 fcvtzs(rd, vn, fbits);
1546 void Fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) {
1550 fcvtzu(rd, vn, fbits);
2307 void Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
2311 scvtf(vd, rn, fbits);
2599 void Ucvtf(const VRegister& vd, const Register& rn, int fbits = 0) {
2603 ucvtf(vd, rn, fbits);
3322 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) {
3325 scvtf(vd, vn, fbits);
[all …]
Dassembler-aarch64.h2419 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0);
2422 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0);
2425 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0);
2428 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0);
2443 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2446 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2449 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
2452 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
/external/skqp/third_party/skcms/
Dskcms.cc1380 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
1383 if (fbits > INT_MAX) { in exp2f_()
1385 } else if (fbits < INT_MIN) { in exp2f_()
1388 int32_t bits = (int32_t)fbits; in exp2f_()
/external/vixl/src/aarch32/
Dassembler-aarch32.cc16279 int32_t fbits) { in vcvt() argument
16287 if (encoded_dt.IsValid() && (fbits >= 1) && (fbits <= 32)) { in vcvt()
16289 uint32_t fbits_ = 64 - fbits; in vcvt()
16299 (((dt2.Is(S16) || dt2.Is(U16)) && (fbits <= 16)) || in vcvt()
16300 ((dt2.Is(S32) || dt2.Is(U32)) && (fbits >= 1) && (fbits <= 32)))) { in vcvt()
16305 uint32_t fbits_ = offset - fbits; in vcvt()
16315 (((dt1.Is(S16) || dt1.Is(U16)) && (fbits <= 16)) || in vcvt()
16316 ((dt1.Is(S32) || dt1.Is(U32)) && (fbits >= 1) && (fbits <= 32)))) { in vcvt()
16321 uint32_t fbits_ = offset - fbits; in vcvt()
16331 if (encoded_dt.IsValid() && (fbits >= 1) && (fbits <= 32)) { in vcvt()
[all …]
Dassembler-aarch32.h418 int32_t fbits);
424 int32_t fbits);
430 int32_t fbits);
4237 int32_t fbits);
4239 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt() argument
4240 vcvt(al, dt1, dt2, rd, rm, fbits); in vcvt()
4248 int32_t fbits);
4250 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in vcvt() argument
4251 vcvt(al, dt1, dt2, rd, rm, fbits); in vcvt()
4259 int32_t fbits);
[all …]
Ddisasm-aarch32.h1683 int32_t fbits);
1690 int32_t fbits);
1697 int32_t fbits);
Ddisasm-aarch32.cc4428 int32_t fbits) { in vcvt() argument
4431 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
4439 int32_t fbits) { in vcvt() argument
4442 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
4450 int32_t fbits) { in vcvt() argument
4453 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
23878 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
23886 fbits); in DecodeT32()
23956 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
23964 fbits); in DecodeT32()
[all …]
/external/skia/third_party/skcms/
Dskcms.cc86 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
94 if (fbits >= (float)INT_MAX) { in exp2f_()
96 } else if (fbits < 0) { in exp2f_()
100 int32_t bits = (int32_t)fbits; in exp2f_()
/external/llvm-project/libclc/generic/lib/math/
Dsincos_helpers.cl204 uint fbits = 224 + 23 - xe;
208 uint shift = 256U - 2 - fbits;
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc4489 { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */
4492 { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */
4525 { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */
4528 { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */
5149 { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */
5152 { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */
5167 { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */
5170 { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */
5173 { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */
5176 { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */
[all …]
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc4489 { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */
4492 { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */
4525 { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */
4528 { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */
5149 { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */
5152 { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */
5167 { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */
5170 { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */
5173 { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */
5176 { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */
[all …]
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3797 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0)
3804 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0)
3811 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0)
3818 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0)
4783 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0)
4790 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
5759 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0)
5766 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0)
/external/skia/third_party/skcms/src/
DTransform_inl.h290 F fbits = (1.0f * (1<<23)) * (x + 121.274057500f in approx_exp2()
293 I32 bits = cast<I32>(max_(fbits, F0)); in approx_exp2()

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