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Searched refs:fcadd (Results 1 – 25 of 28) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dfcadd.s10 fcadd z0.h, p0/m, z0.h, z0.h, #90 label
16 fcadd z0.s, p0/m, z0.s, z0.s, #90 label
22 fcadd z0.d, p0/m, z0.d, z0.d, #90 label
28 fcadd z31.h, p7/m, z31.h, z31.h, #270 label
34 fcadd z31.s, p7/m, z31.s, z31.s, #270 label
40 fcadd z31.d, p7/m, z31.d, z31.d, #270 label
56 fcadd z4.d, p7/m, z4.d, z31.d, #270 label
68 fcadd z4.d, p7/m, z4.d, z31.d, #270 label
Dfcadd-diagnostics.s6 fcadd z0.d, p2/m, z1.d, z2.d, #90 label
15 fcadd z0.d, p8/m, z0.d, z1.d, #90 label
24 fcadd z0.d, p0/m, z0.d, z1.d, #0 label
29 fcadd z0.d, p0/m, z0.d, z1.d, #180 label
34 fcadd z0.d, p0/m, z0.d, z1.d, #450 label
/external/llvm-project/llvm/test/MC/AArch64/
Darmv8.3a-complex.s12 fcadd v0.4h, v1.4h, v2.4h, #90 label
13 fcadd v0.8h, v1.8h, v2.8h, #90 label
14 fcadd v0.2s, v1.2s, v2.2s, #90 label
15 fcadd v0.4s, v1.4s, v2.4s, #90 label
16 fcadd v0.2d, v1.2d, v2.2d, #90 label
17 fcadd v0.2s, v1.2s, v2.2s, #90 label
18 fcadd v0.2s, v1.2s, v2.2s, #270 label
Darmv8.3a-complex_missing.s12 fcadd v0.4h, v1.4h, v2.4h, #90 label
13 fcadd v0.8h, v1.8h, v2.8h, #90 label
14 fcadd v0.2s, v1.2s, v2.2s, #90 label
15 fcadd v0.4s, v1.4s, v2.4s, #90 label
16 fcadd v0.2d, v1.2d, v2.2d, #90 label
17 fcadd v0.2s, v1.2s, v2.2s, #90 label
18 fcadd v0.2s, v1.2s, v2.2s, #270 label
Darmv8.3a-complex_bad.s5 fcadd v0.2s, v1.2s, v2.2s, #1 label
6 fcadd v0.2s, v1.2s, v2.2s, #360 label
7 fcadd v0.2s, v1.2s, v2.2s, #-90 label
8 fcadd v0.2s, v1.2s, v2.2s, #0 label
9 fcadd v0.2s, v1.2s, v2.2s, #180 label
Darmv8.3a-complex_nofp16.s9 fcadd v0.2s, v1.2s, v2.2s, #90 label
10 fcadd v0.4s, v1.4s, v2.4s, #90 label
11 fcadd v0.2d, v1.2d, v2.2d, #90 label
12 fcadd v0.2s, v1.2s, v2.2s, #90 label
13 fcadd v0.2s, v1.2s, v2.2s, #270 label
Darmv8.3a-complex_nofp16_bad.s4 fcadd v0.4h, v1.4h, v2.4h, #90 label
5 fcadd v0.8h, v1.8h, v2.8h, #90 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dneon-vcadd.ll6 ; CHECK-DAG: fcadd v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #90
7 ; CHECK-DAG: fcadd v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #270
17 ; CHECK-DAG: fcadd v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #90
18 ; CHECK-DAG: fcadd v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #270
28 ; CHECK-DAG: fcadd v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #90
29 ; CHECK-DAG: fcadd v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #270
39 ; CHECK-DAG: fcadd v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #90
40 ; CHECK-DAG: fcadd v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #270
50 ; CHECK-DAG: fcadd v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #90
51 ; CHECK-DAG: fcadd v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #270
Dsve-intrinsics-fp-arith.ll115 ; CHECK: fcadd z0.h, p0/m, z0.h, z1.h, #90
117 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %pg,
126 ; CHECK: fcadd z0.s, p0/m, z0.s, z1.s, #270
128 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %pg,
137 ; CHECK: fcadd z0.d, p0/m, z0.d, z1.d, #90
139 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %pg,
1524 declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>,…
1525 declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float…
1526 declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x doub…
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darmv8.3a-complex.txt42 # FP16: fcadd v0.4h, v1.4h, v2.4h, #90
46 # FP16: fcadd v0.8h, v1.8h, v2.8h, #90
50 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
53 # CHECK: fcadd v0.4s, v1.4s, v2.4s, #90
56 # CHECK: fcadd v0.2d, v1.2d, v2.2d, #90
61 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
64 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #270
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1938 fcadd(scratch, pg, scratch, zm, rot); in Fcadd()
1943 fcadd(zd, pg, zd, zm, rot); in Fcadd()
Dlogic-aarch64.cc2725 LogicVRegister Simulator::fcadd(VectorFormat vform, in fcadd() function in vixl::aarch64::Simulator
2761 LogicVRegister Simulator::fcadd(VectorFormat vform, in fcadd() function in vixl::aarch64::Simulator
2767 fcadd<SimFloat16>(vform, dst, src1, src2, rot); in fcadd()
2769 fcadd<float>(vform, dst, src1, src2, rot); in fcadd()
2772 fcadd<double>(vform, dst, src1, src2, rot); in fcadd()
Dsimulator-aarch64.h3295 LogicVRegister fcadd(VectorFormat vform,
3300 LogicVRegister fcadd(VectorFormat vform,
Dassembler-aarch64.h3584 void fcadd(const VRegister& vd,
4087 void fcadd(const ZRegister& zd,
Dsimulator-aarch64.cc5402 fcadd(vf, rd, rn, rm, rot); in VisitNEON3SameExtra()
8105 fcadd(vform, result, zdn, zm, rot); in VisitSVEFPComplexAddition()
Dassembler-sve-aarch64.cc1270 void Assembler::fcadd(const ZRegister& zd, in fcadd() function in vixl::aarch64::Assembler
Dassembler-aarch64.cc3953 void Assembler::fcadd(const VRegister& vd, in fcadd() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h3141 fcadd(vd, vn, vm, rot); in Fcadd()
/external/vixl/test/aarch64/
Dtest-api-movprfx-aarch64.cc330 __ fcadd(z28.VnD(), p5.Merging(), z28.VnD(), z28.VnD(), 90); in TEST() local
849 __ fcadd(z14.VnD(), p7.Merging(), z14.VnD(), z12.VnD(), 90); in TEST() local
1644 __ fcadd(z10.VnH(), p2.Merging(), z10.VnH(), z20.VnH(), 90); in TEST() local
Dtest-disasm-sve-aarch64.cc1357 COMPARE_PREFIX(fcadd(z12.VnH(), p5.Merging(), z12.VnH(), z13.VnH(), 90), in TEST()
1359 COMPARE_PREFIX(fcadd(z12.VnS(), p5.Merging(), z12.VnS(), z13.VnS(), 90), in TEST()
1361 COMPARE_PREFIX(fcadd(z12.VnD(), p5.Merging(), z12.VnD(), z13.VnD(), 90), in TEST()
1363 COMPARE_PREFIX(fcadd(z22.VnH(), p0.Merging(), z22.VnH(), z23.VnH(), 270), in TEST()
1365 COMPARE_PREFIX(fcadd(z22.VnS(), p0.Merging(), z22.VnS(), z23.VnS(), 270), in TEST()
1367 COMPARE_PREFIX(fcadd(z22.VnD(), p0.Merging(), z22.VnD(), z23.VnD(), 270), in TEST()
Dtest-cpu-features-aarch64.cc3534 TEST_FP_FCMA_NEON(fcadd_0, fcadd(v0.V2S(), v1.V2S(), v2.V2S(), 270))
3535 TEST_FP_FCMA_NEON(fcadd_1, fcadd(v0.V4S(), v1.V4S(), v2.V4S(), 90))
3536 TEST_FP_FCMA_NEON(fcadd_2, fcadd(v0.V2D(), v1.V2D(), v2.V2D(), 270))
3774 TEST_FP_FCMA_NEON_NEONHALF(fcadd_0, fcadd(v0.V4H(), v1.V4H(), v2.V4H(), 90))
3775 TEST_FP_FCMA_NEON_NEONHALF(fcadd_1, fcadd(v0.V8H(), v1.V8H(), v2.V8H(), 90))
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12497 "\005fadda\005faddp\005faddv\005fcadd\005fccmp\006fccmpe\005fcmeq\005fcm"
13699 …{ 1095 /* fcadd */, AArch64::FCADDv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
13700 …{ 1095 /* fcadd */, AArch64::FCADDv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
13701 …{ 1095 /* fcadd */, AArch64::FCADDv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_…
13702 …{ 1095 /* fcadd */, AArch64::FCADDv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__…
13703 …{ 1095 /* fcadd */, AArch64::FCADDv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__…
13704 …{ 1095 /* fcadd */, AArch64::FCADD_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie…
13705 …{ 1095 /* fcadd */, AArch64::FCADD_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie…
13706 …{ 1095 /* fcadd */, AArch64::FCADD_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie…
21072 …{ 1095 /* fcadd */, AArch64::FCADDv2f64, Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td216 defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd", int_aarch64_sve_fcadd>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td454 defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd", int_aarch64_sve_fcadd>;
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md3491 void fcadd(const VRegister& vd,

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