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/external/llvm-project/llvm/test/MC/Mips/mips3/
Dinvalid-mips4.s8 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
31 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
33 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
35 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
37 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
39 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
41 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
43 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
45 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
47 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
[all …]
Dinvalid-mips5.s9 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
43 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
45 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
47 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
49 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
51 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
53 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
55 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
57 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
59 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s37 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
39 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
41 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
43 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
45 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
47 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
49 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
51 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
53 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
55 …c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't…
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips2/
Dinvalid-mips32.s8 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
46 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
48 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
50 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
52 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
54 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
56 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
58 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
60 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
62 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
[all …]
Dinvalid-mips32r2.s8 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
14 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
16 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
18 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
20 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
22 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
24 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
26 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
28 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
30 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't e…
[all …]
Dinvalid-mips5.s9 …bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
84 …c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
86 …c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
88 …c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
90 …c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
92 …c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
94 …c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
96 …c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
98 …c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
100 …c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
[all …]
Dinvalid-mips4-wrong-error.s9 …bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exi…
/external/oss-fuzz/projects/libass/
Dass.dict69 "pc.fcc"
97 "tv.fcc"
/external/pcre/dist2/src/
Dpcre2_auto_possess.c308 get_chr_property_list(PCRE2_SPTR code, BOOL utf, BOOL ucp, const uint8_t *fcc, in get_chr_property_list() argument
402 list[3] = fcc[chr]; in get_chr_property_list()
406 list[3] = (chr < 256) ? fcc[chr] : chr; in get_chr_property_list()
408 list[3] = fcc[chr]; in get_chr_property_list()
695 code = get_chr_property_list(code, utf, ucp, cb->fcc, list); in compare_opcodes()
1134 get_chr_property_list(code, utf, ucp, cb->fcc, list) : NULL; in PRIV()
1190 end = get_chr_property_list(code, utf, ucp, cb->fcc, list); in PRIV()
/external/icu/android_icu4j/src/main/java/android/icu/impl/
DNorm2AllModes.java212 public ComposeNormalizer2(Normalizer2Impl ni, boolean fcc) { in ComposeNormalizer2() argument
214 onlyContiguous=fcc; in ComposeNormalizer2()
307 fcc=new ComposeNormalizer2(ni, true); in Norm2AllModes()
314 public final ComposeNormalizer2 fcc; field in Norm2AllModes
/external/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/
DNorm2AllModes.java196 public ComposeNormalizer2(Normalizer2Impl ni, boolean fcc) { in ComposeNormalizer2() argument
198 onlyContiguous=fcc; in ComposeNormalizer2()
288 fcc=new ComposeNormalizer2(ni, true); in Norm2AllModes()
295 public final ComposeNormalizer2 fcc; field in Norm2AllModes
/external/icu/libicu/cts_headers/
Dnorm2allmodes.h222 ComposeNormalizer2(const Normalizer2Impl &ni, UBool fcc) : in ComposeNormalizer2() argument
223 Normalizer2WithImpl(ni), onlyContiguous(fcc) {} in ComposeNormalizer2()
346 : impl(i), comp(*i, false), decomp(*i), fcd(*i), fcc(*i, true) {} in Norm2AllModes()
363 ComposeNormalizer2 fcc; member
/external/icu/icu4c/source/common/
Dnorm2allmodes.h222 ComposeNormalizer2(const Normalizer2Impl &ni, UBool fcc) : in ComposeNormalizer2() argument
223 Normalizer2WithImpl(ni), onlyContiguous(fcc) {} in ComposeNormalizer2()
346 : impl(i), comp(*i, false), decomp(*i), fcd(*i), fcc(*i, true) {} in Norm2AllModes()
363 ComposeNormalizer2 fcc; member
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCondMov.td37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
38 !strconcat(opstr, "\t$rd, $rs, $fcc"),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
48 !strconcat(opstr, "\t$fd, $fs, $fcc"),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMipsInstrFormats.td100 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
830 bits<3> fcc;
837 let Inst{20-18} = fcc;
846 bits<3> fcc;
855 let Inst{10-8} = fcc;
882 bits<3> fcc;
888 let Inst{20-18} = fcc;
899 bits<3> fcc;
905 let Inst{20-18} = fcc;
DMicroMipsInstrFormats.td453 bits<3> fcc;
460 let Inst{15-13} = fcc;
781 bits<3> fcc;
789 let Inst{15-13} = fcc;
801 bits<3> fcc;
808 let Inst{20-18} = fcc; // cc
846 bits<3> fcc;
852 let Inst{15-13} = fcc; //cc
DMipsInstrFPU.td233 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
234 !strconcat(opstr, "\t$fcc, $offset"),
235 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
245 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
246 !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
273 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
274 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
712 // fcc register set is used directly.
713 bits<3> fcc = 0;
719 // fcc register set is used directly.
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsCondMov.td37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
38 !strconcat(opstr, "\t$rd, $rs, $fcc"),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
48 !strconcat(opstr, "\t$fd, $fs, $fcc"),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMipsInstrFormats.td100 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
783 bits<3> fcc;
790 let Inst{20-18} = fcc;
799 bits<3> fcc;
808 let Inst{10-8} = fcc;
835 bits<3> fcc;
841 let Inst{20-18} = fcc;
852 bits<3> fcc;
858 let Inst{20-18} = fcc;
DMicroMipsInstrFormats.td453 bits<3> fcc;
460 let Inst{15-13} = fcc;
781 bits<3> fcc;
789 let Inst{15-13} = fcc;
801 bits<3> fcc;
808 let Inst{20-18} = fcc; // cc
846 bits<3> fcc;
852 let Inst{15-13} = fcc; //cc
DMipsInstrFPU.td236 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
237 !strconcat(opstr, "\t$fcc, $offset"),
238 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
248 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
249 !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
276 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
277 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
745 // fcc register set is used directly.
746 bits<3> fcc = 0;
752 // fcc register set is used directly.
[all …]
/external/llvm/lib/Target/Mips/
DMipsCondMov.td38 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 !strconcat(opstr, "\t$rd, $rs, $fcc"),
40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
48 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 !strconcat(opstr, "\t$fd, $fs, $fcc"),
50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMipsInstrFormats.td812 bits<3> fcc;
819 let Inst{20-18} = fcc;
863 bits<3> fcc;
869 let Inst{20-18} = fcc;
880 bits<3> fcc;
886 let Inst{20-18} = fcc;
/external/icu/icu4j/main/classes/core/src/com/ibm/icu/text/
DNormalizer2.java207 case COMPOSE_CONTIGUOUS: return all2Modes.fcc; in getInstance()
/external/icu/android_icu4j/src/main/java/android/icu/text/
DNormalizer2.java198 case COMPOSE_CONTIGUOUS: return all2Modes.fcc; in getInstance()

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