| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 169 fcvtps h22, h13
170 fcvtps s22, s13
171 fcvtps d21, d14
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| D | arm64-fp-encoding.s | 362 fcvtps w1, h2
363 fcvtps w1, s2
364 fcvtps w1, d2
365 fcvtps x1, h2
366 fcvtps x1, s2
367 fcvtps x1, d2
369 ; FP16: fcvtps w1, h2 ; encoding: [0x41,0x00,0xe8,0x1e]
371 ; NO-FP16-NEXT: fcvtps w1, h2
372 ; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
373 ; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
[all …]
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| D | neon-simd-misc.s | 573 fcvtps v4.4h, v0.4h
574 fcvtps v6.8h, v8.8h
575 fcvtps v6.4s, v8.4s
576 fcvtps v6.2d, v8.2d
577 fcvtps v4.2s, v0.2s
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| D | fullfp16-neon-neg.s | 242 fcvtps h22, h13
338 fcvtps v4.4h, v0.4h
340 fcvtps v6.8h, v8.8h
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| D | arm64-advsimd.s | 876 fcvtps.2s v0, v0
877 fcvtps.4s v0, v0
878 fcvtps.2d v0, v0
879 fcvtps s0, s0
880 fcvtps d0, d0 define
882 ; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e]
883 ; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e]
884 ; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e]
885 ; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e]
886 ; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e]
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| D | neon-diagnostics.s | 5901 fcvtps v0.16b, v31.16b
5902 fcvtps v2.8h, v4.8h
5903 fcvtps v1.8b, v9.8b
5904 fcvtps v13.4h, v21.4h
7267 fcvtps s0, d0
7268 fcvtps d0, s0 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 169 fcvtps h22, h13
170 fcvtps s22, s13
171 fcvtps d21, d14
|
| D | arm64-fp-encoding.s | 362 fcvtps w1, h2
363 fcvtps w1, s2
364 fcvtps w1, d2
365 fcvtps x1, h2
366 fcvtps x1, s2
367 fcvtps x1, d2
369 ; FP16: fcvtps w1, h2 ; encoding: [0x41,0x00,0xe8,0x1e]
371 ; NO-FP16-NEXT: fcvtps w1, h2
372 ; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
373 ; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
[all …]
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| D | neon-simd-misc.s | 573 fcvtps v4.4h, v0.4h
574 fcvtps v6.8h, v8.8h
575 fcvtps v6.4s, v8.4s
576 fcvtps v6.2d, v8.2d
577 fcvtps v4.2s, v0.2s
|
| D | fullfp16-neon-neg.s | 242 fcvtps h22, h13
338 fcvtps v4.4h, v0.4h
340 fcvtps v6.8h, v8.8h
|
| D | arm64-advsimd.s | 876 fcvtps.2s v0, v0
877 fcvtps.4s v0, v0
878 fcvtps.2d v0, v0
879 fcvtps s0, s0
880 fcvtps d0, d0 define
882 ; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e]
883 ; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e]
884 ; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e]
885 ; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e]
886 ; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e]
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| D | neon-diagnostics.s | 5841 fcvtps v0.16b, v31.16b
5842 fcvtps v2.8h, v4.8h
5843 fcvtps v1.8b, v9.8b
5844 fcvtps v13.4h, v21.4h
7036 fcvtps s0, d0
7037 fcvtps d0, s0 define
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| D | basic-a64-instructions.s | 2060 fcvtps wzr, s9
2061 fcvtps x12, s20
2114 fcvtps wzr, d9
2115 fcvtps x12, d20
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 248 ;CHECK: fcvtps w0, s0
250 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %A)
256 ;CHECK: fcvtps x0, s0
258 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)
264 ;CHECK: fcvtps w0, d0
266 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)
272 ;CHECK: fcvtps x0, d0
274 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %A)
278 declare i32 @llvm.aarch64.neon.fcvtps.i32.f32(float) nounwind readnone
279 declare i64 @llvm.aarch64.neon.fcvtps.i64.f32(float) nounwind readnone
[all …]
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| D | fp16_intrinsic_scalar_1op.ll | 5 declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half)
6 declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half)
297 ; CHECK: fcvtps w0, h0
300 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a)
307 ; CHECK: fcvtps x0, h0
310 %vcvtph_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)
|
| D | round-conv.ll | 84 ; CHECK: fcvtps w0, s0
94 ; CHECK: fcvtps x0, s0
104 ; CHECK: fcvtps w0, d0
114 ; CHECK: fcvtps x0, d0
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| D | arm64-vcvt.ll | 176 ;CHECK: fcvtps.2s v0, v0
178 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)
185 ;CHECK: fcvtps.4s v0, v0
187 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)
194 ;CHECK: fcvtps.2d v0, v0
196 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
203 ;CHECK: fcvtps d0, d0
205 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A)
209 declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
210 declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 248 ;CHECK: fcvtps w0, s0
250 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %A)
256 ;CHECK: fcvtps x0, s0
258 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)
264 ;CHECK: fcvtps w0, d0
266 %tmp3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)
272 ;CHECK: fcvtps x0, d0
274 %tmp3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %A)
278 declare i32 @llvm.aarch64.neon.fcvtps.i32.f32(float) nounwind readnone
279 declare i64 @llvm.aarch64.neon.fcvtps.i64.f32(float) nounwind readnone
[all …]
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| D | round-conv.ll | 84 ; CHECK: fcvtps w0, s0
94 ; CHECK: fcvtps x0, s0
104 ; CHECK: fcvtps w0, d0
114 ; CHECK: fcvtps x0, d0
|
| D | arm64-vcvt.ll | 130 ;CHECK: fcvtps.2s v0, v0
132 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)
139 ;CHECK: fcvtps.4s v0, v0
141 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)
148 ;CHECK: fcvtps.2d v0, v0
150 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
154 declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
155 declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
156 declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-cvt.s.cs | 27 0xb6,0xa9,0xa1,0x5e = fcvtps s22, s13
28 0xd5,0xa9,0xe1,0x5e = fcvtps d21, d14
|
| D | neon-simd-misc.s.cs | 171 0x06,0xa9,0xa1,0x4e = fcvtps v6.4s, v8.4s
172 0x06,0xa9,0xe1,0x4e = fcvtps v6.2d, v8.2d
173 0x04,0xa8,0xa1,0x0e = fcvtps v4.2s, v0.2s
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| D | basic-a64-instructions.s.cs | 809 0x3f,0x01,0x28,0x1e = fcvtps wzr, s9
810 0x8c,0x02,0x28,0x9e = fcvtps x12, s20
833 0x3f,0x01,0x68,0x1e = fcvtps wzr, d9
834 0x8c,0x02,0x68,0x9e = fcvtps x12, d20
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| /external/vixl/test/aarch64/ |
| D | test-disasm-fp-aarch64.cc | 311 COMPARE(fcvtps(x28, d29), "fcvtps x28, d29"); in TEST()
312 COMPARE(fcvtps(w30, d31), "fcvtps w30, d31"); in TEST()
315 COMPARE(fcvtps(x4, s5), "fcvtps x4, s5"); in TEST()
316 COMPARE(fcvtps(w6, s7), "fcvtps w6, s7"); in TEST()
368 COMPARE(fcvtps(x4, h5), "fcvtps x4, h5"); in TEST()
369 COMPARE(fcvtps(w6, h7), "fcvtps w6, h7"); in TEST()
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| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 749 fcvtps wzr, h9 label
750 fcvtps x12, h20 label
773 fcvtps wzr, s9 label
774 fcvtps x12, s20 label
797 fcvtps wzr, d9 label
798 fcvtps x12, d20 label
2021 # CHECK-NEXT: 1 3 0.50 fcvtps wzr, h9
2022 # CHECK-NEXT: 1 3 0.50 fcvtps x12, h20
2045 # CHECK-NEXT: 1 3 0.50 fcvtps wzr, s9
2046 # CHECK-NEXT: 1 3 0.50 fcvtps x12, s20
[all …]
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