/external/rust/crates/crossbeam-utils/src/atomic/ |
D | atomic_cell.rs | 335 pub fn fetch_and(&self, val: $t) -> $t { 338 a.fetch_and(val as usize, Ordering::AcqRel) as $t 456 pub fn fetch_and(&self, val: $t) -> $t { 458 a.fetch_and(val, Ordering::AcqRel) 550 pub fn fetch_and(&self, val: bool) -> bool { in fetch_and() method 552 a.fetch_and(val, Ordering::AcqRel) in fetch_and()
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/external/rust/crates/parking_lot/src/ |
D | raw_rwlock.rs | 726 self.state.fetch_and(!WRITER_PARKED_BIT, Ordering::Relaxed); in unlock_shared_slow() 875 self.state.fetch_and(!PARKED_BIT, Ordering::Relaxed); in downgrade_slow() 891 self.state.fetch_and(!PARKED_BIT, Ordering::Relaxed); in downgrade_to_upgradable_slow() 1039 self.state.fetch_and(!PARKED_BIT, Ordering::Relaxed); in wait_for_readers() 1101 self.state.fetch_and(!PARKED_BIT, Ordering::Relaxed); in lock_common()
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D | raw_mutex.rs | 254 self.state.fetch_and(!PARKED_BIT, Ordering::Relaxed); in lock_slow()
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/external/perfetto/src/tracing/ |
D | track_event_category_registry.cc | 60 state_storage_[category_index].fetch_and( in DisableCategoryForInstance()
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/external/rust/crates/futures-core/src/task/__internal/ |
D | atomic_waker.rs | 381 self.state.fetch_and(!WAKING, Release); in take()
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/external/rust/crates/tokio/src/sync/task/ |
D | atomic_waker.rs | 264 self.state.fetch_and(!WAKING, Release); in take_waker()
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/external/rust/crates/futures-util/src/lock/ |
D | mutex.rs | 161 self.state.fetch_and(!HAS_WAITERS, Ordering::Relaxed); // released by mutex unlock in remove_waker() 169 let old_state = self.state.fetch_and(!IS_LOCKED, Ordering::AcqRel); in unlock()
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/external/rust/crates/async-task/src/ |
D | header.rs | 57 .fetch_and(!NOTIFYING & !AWAITER, Ordering::Release); in take()
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D | runnable.rs | 376 let state = (*header).state.fetch_and(!SCHEDULED, Ordering::AcqRel); in drop()
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D | raw.rs | 452 let state = (*raw.header).state.fetch_and(!SCHEDULED, Ordering::AcqRel); in run() 634 .fetch_and(!RUNNING & !SCHEDULED, Ordering::AcqRel); in run()
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/external/rust/crates/tokio/src/sync/ |
D | oneshot.rs | 872 let val = cell.fetch_and(!RX_TASK_SET, AcqRel); in unset_rx_task() 893 let val = cell.fetch_and(!TX_TASK_SET, AcqRel); in unset_tx_task()
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/external/rust/crates/parking_lot_core/src/ |
D | word_lock.rs | 274 self.state.fetch_and(!QUEUE_LOCKED_BIT, Ordering::Release); in unlock_slow()
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/external/libcxx/include/ |
D | atomic | 171 fetch_and(integral op, memory_order m = memory_order_seq_cst) volatile noexcept; 172 integral fetch_and(integral op, memory_order m = memory_order_seq_cst) noexcept; 1025 _Tp fetch_and(_Tp __op, memory_order __m = memory_order_seq_cst) volatile _NOEXCEPT 1028 _Tp fetch_and(_Tp __op, memory_order __m = memory_order_seq_cst) _NOEXCEPT 1068 _Tp operator&=(_Tp __op) volatile _NOEXCEPT {return fetch_and(__op) & __op;} 1070 _Tp operator&=(_Tp __op) _NOEXCEPT {return fetch_and(__op) & __op;} 1573 return __o->fetch_and(__op); 1585 return __o->fetch_and(__op); 1599 return __o->fetch_and(__op, __m); 1611 return __o->fetch_and(__op, __m);
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/external/openscreen/third_party/abseil/src/absl/container/internal/ |
D | hashtablez_sampler.cc | 236 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/libtextclassifier/abseil-cpp/absl/container/internal/ |
D | hashtablez_sampler.cc | 236 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/rust/crates/grpcio-sys/grpc/third_party/abseil-cpp/absl/container/internal/ |
D | hashtablez_sampler.cc | 236 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/webrtc/third_party/abseil-cpp/absl/container/internal/ |
D | hashtablez_sampler.cc | 235 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/angle/third_party/abseil-cpp/absl/container/internal/ |
D | hashtablez_sampler.cc | 239 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/abseil-cpp/absl/container/internal/ |
D | hashtablez_sampler.cc | 235 info->hashes_bitwise_and.fetch_and(hash, std::memory_order_relaxed); in RecordInsertSlow()
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/external/llvm-project/llvm/tools/dsymutil/ |
D | dsymutil.cpp | 655 AllOK.fetch_and( in main() 659 AllOK.fetch_and(verify(OutputFile, Map->getTriple().getArchName(), in main()
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/external/rust/crates/spin/src/ |
D | rw_lock.rs | 261 self.lock.fetch_and(!(WRITER | UPGRADED), Ordering::Release); in force_write_unlock() 703 self.inner.lock.fetch_and(!(WRITER | UPGRADED), Ordering::Release); in drop()
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/external/rust/crates/futures-channel/src/mpsc/ |
D | mod.rs | 1301 self.state.fetch_and(!OPEN_MASK, SeqCst); in set_closed() 1319 self.state.fetch_and(!OPEN_MASK, SeqCst); in set_closed()
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/external/rust/crates/crossbeam-epoch/src/ |
D | atomic.rs | 712 pub fn fetch_and<'g>(&self, val: usize, ord: Ordering, _: &'g Guard) -> Shared<'g, T> { in fetch_and() method 713 unsafe { Shared::from_usize(self.data.fetch_and(val | !low_bits::<T>(), ord)) } in fetch_and()
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/external/llvm-project/libcxx/include/ |
D | atomic | 160 integral fetch_and(integral op, memory_order m = memory_order_seq_cst) volatile noexcept; 161 integral fetch_and(integral op, memory_order m = memory_order_seq_cst) noexcept; 1731 _Tp fetch_and(_Tp __op, memory_order __m = memory_order_seq_cst) volatile _NOEXCEPT 1734 _Tp fetch_and(_Tp __op, memory_order __m = memory_order_seq_cst) _NOEXCEPT 1774 _Tp operator&=(_Tp __op) volatile _NOEXCEPT {return fetch_and(__op) & __op;} 1776 _Tp operator&=(_Tp __op) _NOEXCEPT {return fetch_and(__op) & __op;} 2351 return __o->fetch_and(__op); 2363 return __o->fetch_and(__op); 2377 return __o->fetch_and(__op, __m); 2389 return __o->fetch_and(__op, __m);
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/external/compiler-rt/lib/tsan/rtl/ |
D | tsan_interceptors_mac.cc | 91 OSATOMIC_INTERCEPTORS_BITWISE(OSAtomicAnd, fetch_and, in OSATOMIC_INTERCEPTORS_ARITHMETIC()
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