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Searched refs:fmask (Results 1 – 25 of 72) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dfp16instrinsmc.ll2 …ation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask
17 ; fmask: .ent foo1
18 ; fmask: .set noreorder
19 ; fmask: .set nomacro
20 ; fmask: .set noat
21 ; fmask: .set at
22 ; fmask: .set macro
23 ; fmask: .set reorder
24 ; fmask: .end foo1
38 ; fmask: .ent foo2
[all …]
Dtnaked.ll13 ; CHECK-NOT: .fmask {{.*}}
25 ; CHECK: .fmask 0x00000000,0
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfp16instrinsmc.ll2 …ation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask
17 ; fmask: .ent foo1
18 ; fmask: .set noreorder
19 ; fmask: .set nomacro
20 ; fmask: .set noat
21 ; fmask: .set at
22 ; fmask: .set macro
23 ; fmask: .set reorder
24 ; fmask: .end foo1
38 ; fmask: .ent foo2
[all …]
Dtnaked.ll13 ; CHECK-NOT: .fmask {{.*}}
25 ; CHECK: .fmask 0x00000000,0
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c379 struct radeon_surf fmask = {}; in radeon_winsys_surface_init() local
399 RADEON_SURF_MODE_2D, &fmask)) { in radeon_winsys_surface_init()
404 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in radeon_winsys_surface_init()
406 surf_ws->fmask_size = fmask.surf_size; in radeon_winsys_surface_init()
407 surf_ws->fmask_alignment = MAX2(256, fmask.surf_alignment); in radeon_winsys_surface_init()
408 surf_ws->fmask_tile_swizzle = fmask.tile_swizzle; in radeon_winsys_surface_init()
410 surf_ws->u.legacy.fmask.slice_tile_max = in radeon_winsys_surface_init()
411 (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; in radeon_winsys_surface_init()
412 if (surf_ws->u.legacy.fmask.slice_tile_max) in radeon_winsys_surface_init()
413 surf_ws->u.legacy.fmask.slice_tile_max -= 1; in radeon_winsys_surface_init()
[all …]
/external/llvm/test/MC/Mips/
Dmips-pdr-bad.s29 .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value
30 .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression
31 .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma
32 .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value
33 .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression
34 ….fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement
Dmips-pdr.s14 # ASMOUT: .fmask 0x01010101,-8
48 .fmask 0x01010101,-8
58 .fmask 0x01010101,-8
Delf-tls.s26 .fmask 0x00000000,0
58 .fmask 0x00000000,0
90 .fmask 0x00000000,0
Dmips_gprel16.s25 .fmask 0x00000000,0
49 .fmask 0x00000000,0
Dxgot.s30 .fmask 0x00000000,0
Delf-N64.s28 .fmask 0x90000000,-4
Delf-gprel-32-64.s33 .fmask 0x00000000,0
Ddo_switch1.s21 .fmask 0x00000000,0
/external/llvm-project/llvm/test/MC/Mips/
Dmips-pdr-bad.s29 .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value
30 .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression
31 .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma
32 .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value
33 .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression
34 ….fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement
Dmips-pdr.s14 # ASMOUT: .fmask 0x01010101,-8
48 .fmask 0x01010101,-8
58 .fmask 0x01010101,-8
Delf-tls.s26 .fmask 0x00000000,0
58 .fmask 0x00000000,0
90 .fmask 0x00000000,0
Dmips_gprel16.s25 .fmask 0x00000000,0
49 .fmask 0x00000000,0
Dxgot.s30 .fmask 0x00000000,0
Delf-gprel-32-64.s33 .fmask 0x00000000,0
Delf-N64.s28 .fmask 0x90000000,-4
/external/ltp/testcases/kernel/syscalls/sched_setaffinity/
Dsched_setaffinity01.c31 static cpu_set_t *mask, *emask, *fmask; variable
42 {&self_pid, &mask_size, &fmask, EFAULT},
94 fmask = tst_get_bad_addr(NULL); in setup()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c422 rtex->fmask = new_tex->fmask; in r600_reallocate_texture_inplace()
435 assert(!rtex->fmask.size); in r600_reallocate_texture_inplace()
603 struct radeon_surf fmask = {}; in r600_texture_get_fmask_info() local
612 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw; in r600_texture_get_fmask_info()
613 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh; in r600_texture_get_fmask_info()
614 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea; in r600_texture_get_fmask_info()
615 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split; in r600_texture_get_fmask_info()
618 fmask.u.legacy.bankh = 4; in r600_texture_get_fmask_info()
641 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) { in r600_texture_get_fmask_info()
646 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in r600_texture_get_fmask_info()
[all …]
/external/mesa3d/src/amd/common/
Dac_surface.h125 struct legacy_surf_fmask fmask; member
152 struct gfx9_surf_flags fmask; /* not added to surf_size */ member
Dac_surface.c931 !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 && in gfx6_compute_surface()
1143 surf->u.legacy.fmask.slice_tile_max = (fout.pitch * fout.height) / 64; in gfx6_compute_surface()
1144 if (surf->u.legacy.fmask.slice_tile_max) in gfx6_compute_surface()
1145 surf->u.legacy.fmask.slice_tile_max -= 1; in gfx6_compute_surface()
1147 surf->u.legacy.fmask.tiling_index = fout.tileIndex; in gfx6_compute_surface()
1148 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; in gfx6_compute_surface()
1149 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; in gfx6_compute_surface()
1150 surf->u.legacy.fmask.slice_size = fout.sliceSize; in gfx6_compute_surface()
1257 sin.flags.fmask = 1; in gfx9_get_preferred_swizzle_mode()
1395 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
[all …]
/external/mesa3d/docs/relnotes/
D17.1.3.rst57 - radv: set fmask state to all 0s when no fmask. (v2)

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