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Searched refs:fmaxnm (Results 1 – 25 of 77) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dfmaxnm.s10 fmaxnm z0.h, p0/m, z0.h, #0.000000000000000 label
16 fmaxnm z0.h, p0/m, z0.h, #0.0 label
22 fmaxnm z0.s, p0/m, z0.s, #0.0 label
28 fmaxnm z0.d, p0/m, z0.d, #0.0 label
34 fmaxnm z31.h, p7/m, z31.h, #1.000000000000000 label
40 fmaxnm z31.h, p7/m, z31.h, #1.0 label
46 fmaxnm z31.s, p7/m, z31.s, #1.0 label
52 fmaxnm z31.d, p7/m, z31.d, #1.0 label
58 fmaxnm z0.h, p7/m, z0.h, z31.h label
64 fmaxnm z0.s, p7/m, z0.s, z31.s label
[all …]
Dfmaxnm-diagnostics.s6 fmaxnm z0.h, p0/m, z0.h, #0.5 label
11 fmaxnm z0.h, p0/m, z0.h, #-0.0 label
16 fmaxnm z0.h, p0/m, z0.h, #0.0000000000000000000000001 label
21 fmaxnm z0.h, p0/m, z0.h, #1.0000000000000000000000001 label
26 fmaxnm z0.h, p0/m, z0.h, #0.9999999999999999999999999 label
35 fmaxnm z0.h, p7/m, z1.h, z31.h label
44 fmaxnm z0.b, p7/m, z0.b, z31.b label
49 fmaxnm z0.h, p7/m, z0.h, z31.s label
58 fmaxnm z0.h, p8/m, z0.h, z31.h label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-vminmaxnm.ll4 ; CHECK: fmaxnm.2s v0, v0, v1
6 …%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b)…
11 ; CHECK: fmaxnm.4s v0, v0, v1
13 …%vmaxnm2.i = tail call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b)…
18 ; CHECK: fmaxnm.2d v0, v0, v1
20 …%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> …
46 ; CHECK: fmaxnm s0, s0, s1
48 %vmaxnm2.i = tail call float @llvm.aarch64.neon.fmaxnm.f32(float %a, float %b) nounwind
62 declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
[all …]
Dknown-never-nan.ll4 ; This should codegen to fmaxnm with no-signed-zeros.
5 define float @fmaxnm(i32 %i1, i32 %i2) #0 {
6 ; CHECK-LABEL: fmaxnm:
27 ; Therefore, this is not fmaxnm.
Dsve-fixed-length-fp-minmax.ll30 ; CHECK: fmaxnm v0.4h, v0.4h, v1.4h
39 ; CHECK: fmaxnm v0.8h, v0.8h, v1.8h
50 ; CHECK-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
65 ; VBITS_GE_512-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
77 ; VBITS_EQ_256-DAG: fmaxnm [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP1_LO]].h, [[OP2_LO]].h
78 ; VBITS_EQ_256-DAG: fmaxnm [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP1_HI]].h, [[OP2_HI]].h
94 ; VBITS_GE_1024-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
109 ; VBITS_GE_2048-NEXT: fmaxnm [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h
122 ; CHECK: fmaxnm v0.2s, v0.2s, v1.2s
131 ; CHECK: fmaxnm v0.4s, v0.4s, v1.4s
[all …]
Dvecreduce-fmax-legalization-nan.ll65 ; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
66 ; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
67 ; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
Dvecreduce-fmax-legalization.ll82 ; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
83 ; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
84 ; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
Dselect_fmf.ll7 ; CHECK-NEXT: fmaxnm s2, s0, s3
45 ; CHECK-NEXT: fmaxnm s2, s0, s3
Dsve-intrinsics-fp-arith-merging.ll94 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
97 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
106 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
109 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
118 ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d
121 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
347 declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>…
348 declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x floa…
349 declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x dou…
Darm64-neon-add-sub.ll205 ; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
233 declare <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double>, <1 x double>)
Dsve-fp.ll601 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z2.h
602 ; CHECK-NEXT: fmaxnm z1.h, p0/m, z1.h, z3.h
612 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
622 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
632 ; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h
642 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z2.s
643 ; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z3.s
653 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
663 ; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s
673 ; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z2.d
[all …]
Dsve-intrinsics-fp-arith.ll387 ; CHECK: fmaxnm z0.h, p0/m, z0.h, z1.h
389 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
397 ; CHECK: fmaxnm z0.s, p0/m, z0.s, z1.s
399 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
407 ; CHECK: fmaxnm z0.d, p0/m, z0.d, z1.d
409 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
1555 declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>…
1556 declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x floa…
1557 declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x dou…
/external/llvm/test/CodeGen/AArch64/
Darm64-vminmaxnm.ll4 ; CHECK: fmaxnm.2s v0, v0, v1
6 …%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b)…
11 ; CHECK: fmaxnm.4s v0, v0, v1
13 …%vmaxnm2.i = tail call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b)…
18 ; CHECK: fmaxnm.2d v0, v0, v1
20 …%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> …
46 ; CHECK: fmaxnm s0, s0, s1
48 %vmaxnm2.i = tail call float @llvm.aarch64.neon.fmaxnm.f32(float %a, float %b) nounwind
62 declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
[all …]
Darm64-neon-add-sub.ll205 ; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
233 declare <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double>, <1 x double>)
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-max-min.s100 fmaxnm v0.4h, v1.4h, v2.4h
101 fmaxnm v0.8h, v1.8h, v2.8h
102 fmaxnm v0.2s, v1.2s, v2.2s
103 fmaxnm v31.4s, v15.4s, v16.4s
104 fmaxnm v7.2d, v8.2d, v25.2d
Darm64-fp-encoding.s53 fmaxnm h1, h2, h3
54 fmaxnm s1, s2, s3
55 fmaxnm d1, d2, d3 define
62 ; FP16: fmaxnm h1, h2, h3 ; encoding: [0x41,0x68,0xe3,0x1e]
64 ; NO-FP16-NEXT: fmaxnm h1, h2, h3
65 ; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
66 ; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
Dfullfp16-neon-neg.s200 fmaxnm v0.4h, v1.4h, v2.4h
202 fmaxnm v0.8h, v1.8h, v2.8h
/external/llvm/test/MC/AArch64/
Dneon-max-min.s100 fmaxnm v0.4h, v1.4h, v2.4h
101 fmaxnm v0.8h, v1.8h, v2.8h
102 fmaxnm v0.2s, v1.2s, v2.2s
103 fmaxnm v31.4s, v15.4s, v16.4s
104 fmaxnm v7.2d, v8.2d, v25.2d
Darm64-fp-encoding.s53 fmaxnm h1, h2, h3
54 fmaxnm s1, s2, s3
55 fmaxnm d1, d2, d3 define
62 ; FP16: fmaxnm h1, h2, h3 ; encoding: [0x41,0x68,0xe3,0x1e]
64 ; NO-FP16-NEXT: fmaxnm h1, h2, h3
65 ; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
66 ; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
Dfullfp16-neon-neg.s200 fmaxnm v0.4h, v1.4h, v2.4h
202 fmaxnm v0.8h, v1.8h, v2.8h
/external/capstone/suite/MC/AArch64/
Dneon-max-min.s.cs32 0x20,0xc4,0x22,0x0e = fmaxnm v0.2s, v1.2s, v2.2s
33 0xff,0xc5,0x30,0x4e = fmaxnm v31.4s, v15.4s, v16.4s
34 0x07,0xc5,0x79,0x4e = fmaxnm v7.2d, v8.2d, v25.2d
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt50 # FP16: fmaxnm h1, h2, h3
51 # CHECK: fmaxnm s1, s2, s3
52 # CHECK: fmaxnm d1, d2, d3
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt50 # FP16: fmaxnm h1, h2, h3
51 # CHECK: fmaxnm s1, s2, s3
52 # CHECK: fmaxnm d1, d2, d3
/external/vixl/test/aarch64/
Dtest-disasm-fp-aarch64.cc159 COMPARE(fmaxnm(h4, h5, h6), "fmaxnm h4, h5, h6"); in TEST()
160 COMPARE(fmaxnm(s31, s0, s1), "fmaxnm s31, s0, s1"); in TEST()
161 COMPARE(fmaxnm(d2, d3, d4), "fmaxnm d2, d3, d4"); in TEST()
/external/vixl/doc/
Dchangelog.md98 + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,

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