Searched refs:fminnmv (Results 1 – 25 of 52) sorted by relevance
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3 fminnmv b0, p7, z31.b label12 fminnmv h0, p8, z31.h label17 fminnmv h0, p7.b, z31.h label22 fminnmv h0, p7.q, z31.h label31 fminnmv v0, p7, z31.h label40 fminnmv d0, p7, z31.d define46 fminnmv d0, p7, z31.d define
10 fminnmv h0, p7, z31.h label16 fminnmv s0, p7, z31.s label22 fminnmv d0, p7, z31.d define
56 %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> %in)62 ; CHECK: fminnmv s0, v0.4s63 %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %in)70 %minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)74 declare float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float>)75 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)76 declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)
140 ; CHECK: fminnmv h0, p0, z0.h142 %res = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %pg,149 ; CHECK: fminnmv s0, p0, z0.s151 %res = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %pg,158 ; CHECK: fminnmv d0, p0, z0.d160 %res = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %pg,212 declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)213 declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)214 declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)
53 ; CHECK-NEXT: fminnmv s0, v0.4s65 ; CHECK-NEXT: fminnmv s0, v0.4s85 ; CHECK-NEXT: fminnmv s0, v0.4s
710 ; CHECK: fminnmv h0, v0.4h719 ; CHECK: fminnmv h0, v0.8h729 ; CHECK-NEXT: fminnmv h0, [[PG]], [[OP]].h740 ; VBITS_GE_512-NEXT: fminnmv h0, [[PG]], [[OP]].h749 ; VBITS_EQ_256-DAG: fminnmv h0, [[PG]], [[MIN]].h760 ; VBITS_GE_1024-NEXT: fminnmv h0, [[PG]], [[OP]].h771 ; VBITS_GE_2048-NEXT: fminnmv h0, [[PG]], [[OP]].h790 ; CHECK: fminnmv s0, v0.4s800 ; CHECK-NEXT: fminnmv s0, [[PG]], [[OP]].s811 ; VBITS_GE_512-NEXT: fminnmv s0, [[PG]], [[OP]].s[all …]
78 %min = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)83 declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)
3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)455 ; CHECK: fminnmv s{{[0-9]+}}, {{v[0-9]+}}.4s457 %0 = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %a)
127 ; CHECK: fminnmv
306 ; CHECK: fminnmv
94 fminnmv h0, v1.4h98 fminnmv h0, v1.8h102 fminnmv s0, v1.4s
74 fminnmv h0, v1.8h
3818 fminnmv b0, v1.16b3836 fminnmv h0, v1.8h3854 fminnmv d0, v1.2d define
3758 fminnmv b0, v1.16b3776 fminnmv h0, v1.8h3794 fminnmv d0, v1.2d define
38 0x20,0xc8,0xb0,0x6e = fminnmv s0, v1.4s
232 ; CODE: fminnmv s0, v0.4s
3025 void fminnmv(const VRegister& vd, const VRegister& vn);4278 void fminnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
5618 fminnmv(vf, rd, rn); in VisitNEONAcrossLanes()5638 fminnmv(vf, rd, rn); in VisitNEONAcrossLanes()8201 fn = &Simulator::fminnmv; in VisitSVEFPFastReduction()
1435 COMPARE_PREFIX(fminnmv(h20, p6, z21.VnH()), "fminnmv h20, p6, z21.h"); in TEST()1436 COMPARE_PREFIX(fminnmv(s20, p6, z21.VnS()), "fminnmv s20, p6, z21.s"); in TEST()1437 COMPARE_PREFIX(fminnmv(d20, p6, z21.VnD()), "fminnmv d20, p6, z21.d"); in TEST()
3269 TEST_FP_NEON(fminnmv_0, fminnmv(s0, v1.V4S()))3668 TEST_FP_NEON_NEONHALF(fminnmv_0, fminnmv(h0, v1.V4H()))3669 TEST_FP_NEON_NEONHALF(fminnmv_1, fminnmv(h0, v1.V8H()))