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/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3rf_4rf.ll67 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
72 declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind
78 ; CHECK: fmsub.w
92 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
97 declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind
103 ; CHECK: fmsub.d
/external/llvm/test/CodeGen/Mips/msa/
D3rf_4rf.ll67 %3 = tail call <4 x float> @llvm.mips.fmsub.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
72 declare <4 x float> @llvm.mips.fmsub.w(<4 x float>, <4 x float>, <4 x float>) nounwind
78 ; CHECK: fmsub.w
92 %3 = tail call <2 x double> @llvm.mips.fmsub.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
97 declare <2 x double> @llvm.mips.fmsub.d(<2 x double>, <2 x double>, <2 x double>) nounwind
103 ; CHECK: fmsub.d
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfp-dp3.ll21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
22 ; CHECK-NOFAST: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
61 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK-NOFAST: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
104 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
105 ; CHECK-NOFAST-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
157 ; CHECK-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
Darm64-fmadd.ll23 ; CHECK: fmsub s0, s0, s1, s2
32 ; CHECK: fmsub s0, s1, s0, s2
66 ; CHECK: fmsub d0, d0, d1, d2
75 ; CHECK: fmsub d0, d1, d0, d2
Dfp16_intrinsic_scalar_3op.ll23 ; CHECK: fmsub h0, h0, h1, h2
32 ; CHECK: fmsub h0, h1, h0, h2
52 ; CHECK: fmsub h0, h0, h1, h2
Daarch64-a57-fp-load-balancing.ll32 ; CHECK: fmsub [[x]]
81 ; CHECK: fmsub [[x]]
130 ; CHECK: fmsub [[x]]
176 ; CHECK: fmsub [[x]]
225 ; CHECK: fmsub [[x]]
266 ; CHECK: fmsub [[x]]
/external/llvm/test/CodeGen/AArch64/
Dfp-dp3.ll21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
22 ; CHECK-NOFAST: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
61 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK-NOFAST: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
104 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
105 ; CHECK-NOFAST-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
157 ; CHECK-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
Darm64-fmadd.ll23 ; CHECK: fmsub s0, s0, s1, s2
32 ; CHECK: fmsub s0, s1, s0, s2
66 ; CHECK: fmsub d0, d0, d1, d2
75 ; CHECK: fmsub d0, d1, d0, d2
Daarch64-a57-fp-load-balancing.ll32 ; CHECK: fmsub [[x]]
81 ; CHECK: fmsub [[x]]
130 ; CHECK: fmsub [[x]]
176 ; CHECK: fmsub [[x]]
225 ; CHECK: fmsub [[x]]
266 ; CHECK: fmsub [[x]]
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-fp.s.cs63 0xfc,0x43,0x29,0x38 = fmsub 2, 3, 4, 5
64 0xfc,0x43,0x29,0x39 = fmsub. 2, 3, 4, 5
/external/llvm-project/llvm/test/MC/RISCV/
Drv32f-valid.s47 # CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7, dyn
49 fmsub.s f14, f15, f16, f17, dyn
123 # CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7, rtz
125 fmsub.s f14, f15, f16, f17, rtz
135 # CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7
137 fmsub.s f14, f15, f16, f17, dyn
Drv32zfh-valid.s47 # CHECK-ASM-AND-OBJ: fmsub.h fa4, fa5, fa6, fa7, dyn
49 fmsub.h f14, f15, f16, f17, dyn
123 # CHECK-ASM-AND-OBJ: fmsub.h fa4, fa5, fa6, fa7, rtz
125 fmsub.h f14, f15, f16, f17, rtz
135 # CHECK-ASM-AND-OBJ: fmsub.h fa4, fa5, fa6, fa7
137 fmsub.h f14, f15, f16, f17, dyn
Drvd-aliases-valid.s60 # CHECK-INST: fmsub.d fa4, fa5, fa6, fa7, dyn
61 # CHECK-ALIAS: fmsub.d fa4, fa5, fa6, fa7{{[[:space:]]}}
62 fmsub.d f14, f15, f16, f17
Drv32d-valid.s52 # CHECK-ASM-AND-OBJ: fmsub.d fa4, fa5, fa6, fa7, dyn
54 fmsub.d f14, f15, f16, f17, dyn
127 # CHECK-ASM-AND-OBJ: fmsub.d fa4, fa5, fa6, fa7, rtz
129 fmsub.d f14, f15, f16, f17, rtz
Drvzfh-aliases-valid.s64 # CHECK-INST: fmsub.h fa4, fa5, fa6, fa7, dyn
65 # CHECK-ALIAS: fmsub.h fa4, fa5, fa6, fa7{{[[:space:]]}}
66 fmsub.h f14, f15, f16, f17
Drvf-aliases-valid.s123 # CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn
124 # CHECK-ALIAS: fmsub.s fa4, fa5, fa6, fa7{{[[:space:]]}}
125 fmsub.s f14, f15, f16, f17
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s206 # CHECK-BE: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38]
207 # CHECK-LE: fmsub 2, 3, 4, 5 # encoding: [0x38,0x29,0x43,0xfc]
208 fmsub 2, 3, 4, 5
209 # CHECK-BE: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39]
210 # CHECK-LE: fmsub. 2, 3, 4, 5 # encoding: [0x39,0x29,0x43,0xfc]
211 fmsub. 2, 3, 4, 5
/external/llvm-project/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s212 # CHECK-BE: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38]
213 # CHECK-LE: fmsub 2, 3, 4, 5 # encoding: [0x38,0x29,0x43,0xfc]
214 fmsub 2, 3, 4, 5
215 # CHECK-BE: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39]
216 # CHECK-LE: fmsub. 2, 3, 4, 5 # encoding: [0x39,0x29,0x43,0xfc]
217 fmsub. 2, 3, 4, 5
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfp-contract.ll2 ; option is set (the same applies for fmul, fsub and fmsub).
40 ; CHECK-CONTRACT-FAST: fmsub.w
/external/llvm/test/MC/Mips/msa/
Dtest_3rf.s43 # CHECK: fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b]
44 # CHECK: fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b]
126 fmsub.w $w17, $w25, $w0
127 fmsub.d $w8, $w18, $w16
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_3rf.s43 # CHECK: fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b]
44 # CHECK: fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b]
126 fmsub.w $w17, $w25, $w0
127 fmsub.d $w8, $w18, $w16
/external/capstone/suite/MC/Mips/
Dtest_3rf.s.cs42 0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0
43 0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16
/external/llvm/test/MC/AArch64/
Darm64-fp-encoding.s86 fmsub h1, h2, h3, h4
87 fmsub s1, s2, s3, s4
88 fmsub d1, d2, d3, d4 define
90 ; FP16: fmsub h1, h2, h3, h4 ; encoding: [0x41,0x90,0xc3,0x1f]
92 ; NO-FP16-NEXT: fmsub h1, h2, h3, h4
93 ; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f]
94 ; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-fp-encoding.s86 fmsub h1, h2, h3, h4
87 fmsub s1, s2, s3, s4
88 fmsub d1, d2, d3, d4 define
90 ; FP16: fmsub h1, h2, h3, h4 ; encoding: [0x41,0x90,0xc3,0x1f]
92 ; NO-FP16-NEXT: fmsub h1, h2, h3, h4
93 ; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f]
94 ; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f]
/external/llvm/test/CodeGen/PowerPC/
Dfma-assoc.ll50 ; CHECK: fmsub
167 ; CHECK: fmsub
186 ; CHECK: fmsub

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