Home
last modified time | relevance | path

Searched refs:fp64 (Results 1 – 25 of 455) sorted by relevance

12345678910>>...19

/external/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/
Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
68 ; CHECK-NEXT: fp64-fp16-input-denormals: true
69 ; CHECK-NEXT: fp64-fp16-output-denormals: true
98 ; CHECK-NEXT: fp64-fp16-input-denormals: true
99 ; CHECK-NEXT: fp64-fp16-output-denormals: true
128 ; CHECK-NEXT: fp64-fp16-input-denormals: true
129 ; CHECK-NEXT: fp64-fp16-output-denormals: true
142 ; CHECK-NEXT: fp64-fp16-input-denormals: true
143 ; CHECK-NEXT: fp64-fp16-output-denormals: true
[all …]
Dmachine-function-info-no-ir.mir32 # FULL-NEXT: fp64-fp16-input-denormals: true
33 # FULL-NEXT: fp64-fp16-output-denormals: true
102 # FULL-NEXT: fp64-fp16-input-denormals: true
103 # FULL-NEXT: fp64-fp16-output-denormals: true
143 # FULL-NEXT: fp64-fp16-input-denormals: true
144 # FULL-NEXT: fp64-fp16-output-denormals: true
185 # FULL-NEXT: fp64-fp16-input-denormals: true
186 # FULL-NEXT: fp64-fp16-output-denormals: true
256 # ALL-NEXT: fp64-fp16-input-denormals: false
257 # ALL-NEXT: fp64-fp16-output-denormals: false
[all …]
/external/FP16/include/fp16/
Dbitcasts.h69 } fp64 = { w }; in fp64_from_bits()
70 return fp64.as_value; in fp64_from_bits()
87 } fp64 = { f }; in fp64_to_bits()
88 return fp64.as_bits; in fp64_to_bits()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fmad.s64.mir10 fp64-fp16-output-denormals: false
11 fp64-fp16-input-denormals: false
35 fp64-fp16-input-denormals: false
36 fp64-fp16-output-denormals: false
66 fp64-fp16-input-denormals: true
67 fp64-fp16-output-denormals: true
91 fp64-fp16-input-denormals: true
92 fp64-fp16-output-denormals: true
Dinst-select-fcanonicalize.mir12 fp64-fp16-input-denormals: true
13 fp64-fp16-output-denormals: true
39 fp64-fp16-input-denormals: false
40 fp64-fp16-output-denormals: false
120 fp64-fp16-input-denormals: true
121 fp64-fp16-output-denormals: true
147 fp64-fp16-input-denormals: false
148 fp64-fp16-output-denormals: false
174 fp64-fp16-input-denormals: true
175 fp64-fp16-output-denormals: true
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfp64a.ll10 ; RUN: not --crash llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=…
11 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-F…
12 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=AL…
13 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO…
14 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=…
16 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP6…
17 ; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -…
18 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-F…
19 ; RUN: not --crash llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s…
Dfp-contract.ll4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \
8 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \
/external/llvm/test/CodeGen/AMDGPU/
Dhsa-fp-mode.ll65 attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-denormals" }
66 attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-denormals" }
67 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
68 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
Ddefault-fp-mode.ll59 attributes #2 = { nounwind "target-features"="+fp64-denormals" }
61 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
62 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
/external/llvm/test/CodeGen/Mips/
Dfp64a.ll14 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-F…
15 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=AL…
16 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO…
17 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=…
19 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP6…
20 ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-pr…
21 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-F…
22 ; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-…
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
/external/llvm-project/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
Dmicromips-fpu64-instructions.s1 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips,fp64 \
3 # RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips,fp64 \
/external/llvm/test/CodeGen/Mips/msa/
Dllvm-stress-sz1-s742806235.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
D2r_vector_scalar.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
Delm_move.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
Dllvm-stress-s2501752154-simplified.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Dllvm-stress-sz1-s742806235.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
D2r_vector_scalar.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
Delm_move.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
Dllvm-stress-s2501752154-simplified.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
/external/llvm-project/lld/test/ELF/
Dmips-fp-flags-err.test9 # RUN: yaml2obj --docnum=4 %s -o %t-fp64.o
14 # RUN: not ld.lld %t-dbl.o %t-fp64.o -shared -o /dev/null 2>&1 \
26 # DBLFP64: {{.*}}fp64.o: floating point ABI '-mgp32 -mfp64' is incompatible with target floating po…
88 # fp64.o
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-fpxx1.ll1 ; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
2 ; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-vmov-pair.txt1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encodi…
5 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encodi…
/external/llvm-project/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-fpxx1.ll1 ; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s \
3 ; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \

12345678910>>...19