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Searched refs:fpr16 (Results 1 – 21 of 21) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-frint-nofp16.mir18 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
21 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
52 ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
53 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
54 ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2
55 ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3
58 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
61 ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
64 ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
67 ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
[all …]
Dselect-unmerge.mir117 ; CHECK: %2:fpr16 = COPY [[INS_SHARED]].hsub
118 ; CHECK: %3:fpr16 = CPYi16 [[INS_SHARED]], 1
119 ; CHECK: %4:fpr16 = CPYi16 [[INS2]], 2
120 ; CHECK: %5:fpr16 = CPYi16 [[INS3]], 3
151 ; CHECK: %2:fpr16 = COPY %0.hsub
152 ; CHECK: %3:fpr16 = CPYi16 %0, 1
153 ; CHECK: %4:fpr16 = CPYi16 %0, 2
154 ; CHECK: %5:fpr16 = CPYi16 %0, 3
155 ; CHECK: %6:fpr16 = CPYi16 %0, 4
156 ; CHECK: %7:fpr16 = CPYi16 %0, 5
[all …]
Dpreselect-process-phis.mir29 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
81 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
84 ; CHECK: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
85 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
Dfp16-copy-gpr.mir48 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
49 ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
92 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
119 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
Dselect-extract-vector-elt.mir107 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
130 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
153 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
177 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
201 ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
Dselect-insert-extract.mir101 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
104 ; CHECK: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]].hsub
Dselect-fp16-fconstant.mir12 ; CHECK: [[FMOVH0_:%[0-9]+]]:fpr16 = FMOVH0
Dselect-nearbyint.mir156 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
157 ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = FRINTIHr [[COPY]]
Dselect-fp-casts.mir19 ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
41 ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
126 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
148 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
Dselect-intrinsic-trunc.mir66 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
67 ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = FRINTZHr [[COPY]]
Dselect-frint.mir18 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
19 ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = FRINTXHr [[COPY]]
Dselect-intrinsic-round.mir66 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
67 ; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = FRINTAHr [[COPY]]
Dselect-reduce-add.mir49 ; CHECK: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]]
Dselect-dup.mir151 ; CHECK: %copy:fpr16 = COPY $h0
194 ; CHECK: %copy:fpr16 = COPY $h0
Dcontract-store.mir86 ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
Dstore-addressing-modes.mir116 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0
Dselect-insert-vector-elt.mir41 ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
Dselect-load.mir363 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
461 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
Dload-wro-addressing-modes.mir316 ; CHECK: %load:fpr16 = LDRHroW %base, %foo, 1, 1 :: (load 2)
Dload-addressing-modes.mir578 ; CHECK: [[LDRHroX:%[0-9]+]]:fpr16 = LDRHroX [[COPY]], [[COPY1]], 0, 0 :: (load 2 from %ir.addr)
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_ppc64.h104 uintptr_t fpr16; member
183 static_assert(offsetof(marl_fiber_context, fpr16) == MARL_REG_FPR16,