| /external/mesa3d/src/panfrost/midgard/ |
| D | midgard_opt_perspective.c | 68 unsigned frcp = ins->src[1]; in midgard_opt_combine_projection() local
71 if (frcp & PAN_IS_REG) continue; in midgard_opt_combine_projection()
79 if (sub->dest != frcp) continue; in midgard_opt_combine_projection()
93 if (!mir_single_use(ctx, frcp)) continue; in midgard_opt_combine_projection()
|
| D | midgard_compile.c | 702 ALU_CASE(frcp, frcp); in emit_alu()
|
| /external/llvm/test/MC/Mips/msa/ |
| D | test_2rf.s | 21 # CHECK: frcp.w $w19, $w0 # encoding: [0x7b,0x2a,0x04,0xde]
22 # CHECK: frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e]
54 frcp.w $w19, $w0
55 frcp.d $w4, $w14
|
| /external/llvm-project/llvm/test/MC/Mips/msa/ |
| D | test_2rf.s | 21 # CHECK: frcp.w $w19, $w0 # encoding: [0x7b,0x2a,0x04,0xde]
22 # CHECK: frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e]
54 frcp.w $w19, $w0
55 frcp.d $w4, $w14
|
| /external/capstone/suite/MC/Mips/ |
| D | test_2rf.s.cs | 20 0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0
21 0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_2rf.txt | 21 0x7b 0x2a 0x04 0xde # CHECK: frcp.w $w19, $w0
22 0x7b 0x2b 0x71 0x1e # CHECK: frcp.d $w4, $w14
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_2rf.txt | 21 0x7b 0x2a 0x04 0xde # CHECK: frcp.w $w19, $w0
22 0x7b 0x2b 0x71 0x1e # CHECK: frcp.d $w4, $w14
|
| /external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
| D | 2rf.ll | 168 %1 = tail call <4 x float> @llvm.mips.frcp.w(<4 x float> %0)
173 declare <4 x float> @llvm.mips.frcp.w(<4 x float>) nounwind
178 ; CHECK-DAG: frcp.w [[WD:\$w[0-9]+]], [[WS]]
189 %1 = tail call <2 x double> @llvm.mips.frcp.d(<2 x double> %0)
194 declare <2 x double> @llvm.mips.frcp.d(<2 x double>) nounwind
199 ; CHECK-DAG: frcp.d [[WD:\$w[0-9]+]], [[WS]]
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | 2rf.ll | 168 %1 = tail call <4 x float> @llvm.mips.frcp.w(<4 x float> %0)
173 declare <4 x float> @llvm.mips.frcp.w(<4 x float>) nounwind
178 ; CHECK-DAG: frcp.w [[WD:\$w[0-9]+]], [[WS]]
189 %1 = tail call <2 x double> @llvm.mips.frcp.d(<2 x double> %0)
194 declare <2 x double> @llvm.mips.frcp.d(<2 x double>) nounwind
199 ; CHECK-DAG: frcp.d [[WD:\$w[0-9]+]], [[WS]]
|
| /external/llvm-project/llvm/test/MC/Mips/mips32r2/ |
| D | invalid-msa.s | 31 …frcp.d $w12,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
32 …frcp.w $w30,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | invalid-msa.s | 31 …frcp.d $w12,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
32 …frcp.w $w30,$w8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_emit.c | 68 OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
|
| /external/mesa3d/docs/relnotes/ |
| D | 11.1.1.rst | 110 - nir: Add a lower_fdiv option, turn fdiv into fmul/frcp.
|
| D | 20.1.0.rst | 614 - pan/bi: Add fp16 support for frcp/frsq
|
| /external/mesa3d/src/panfrost/bifrost/ |
| D | bifrost_compile.c | 1682 bi_instruction frcp = { in bi_lower_cube_coord() local
1696 .src = { frcp.dest, BIR_INDEX_CONSTANT | 0, BIR_INDEX_ZERO }, in bi_lower_cube_coord()
1727 bi_emit(ctx, frcp); in bi_lower_cube_coord()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 470 // frcp.[wd], frsqrt.[wd]
|
| D | MipsScheduleGeneric.td | 1583 // fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw]
|
| D | MipsMSAInstrInfo.td | 2134 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2135 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 471 // frcp.[wd], frsqrt.[wd]
|
| D | MipsScheduleGeneric.td | 1586 // fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw]
|
| D | MipsMSAInstrInfo.td | 2134 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2135 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
|
| /external/icu/icu4c/source/data/misc/ |
| D | metadata.txt | 2223 frcp{
|
| D | supplementalData.txt | 7970 "frcp",
20879 "frcp",
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 2115 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2116 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 5013 "fmsub.d\007fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007f"
6655 …{ 4637 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
6656 …{ 4644 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasM…
9925 { 4637 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9926 { 4644 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
|