| /external/llvm-project/llvm/test/MC/AArch64/SVE/ |
| D | frecpx.s | 10 frecpx z31.h, p7/m, z31.h label
16 frecpx z31.s, p7/m, z31.s label
22 frecpx z31.d, p7/m, z31.d label
38 frecpx z4.d, p7/m, z31.d label
50 frecpx z4.d, p7/m, z31.d label
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| D | frecpx-diagnostics.s | 3 frecpx z0.b, p0/m, z0.b label
8 frecpx z0.s, p0/z, z0.s label
13 frecpx z0.s, p8/m, z0.s label
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-scalar-recip.s | 45 frecpx h18, h10
46 frecpx s18, s10
47 frecpx d16, d19
|
| D | fullfp16-neon-neg.s | 288 frecpx h18, h10
|
| D | neon-diagnostics.s | 234 frecpx s18, h10
235 frecpx d16, s19
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-recip.s | 45 frecpx h18, h10
46 frecpx s18, s10
47 frecpx d16, d19
|
| D | fullfp16-neon-neg.s | 288 frecpx h18, h10
|
| D | neon-diagnostics.s | 234 frecpx s18, h10
235 frecpx d16, s19
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-recip.s.cs | 8 0x52,0xf9,0xa1,0x5e = frecpx s18, s10
9 0x70,0xfa,0xe1,0x5e = frecpx d16, d19
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 114 ;CHECK: frecpx s0, {{s[0-9]+}}
116 %tmp3 = call float @llvm.aarch64.neon.frecpx.f32(float %tmp1)
122 ;CHECK: frecpx d0, {{d[0-9]+}}
124 %tmp3 = call double @llvm.aarch64.neon.frecpx.f64(double %tmp1)
128 declare float @llvm.aarch64.neon.frecpx.f32(float) nounwind readnone
129 declare double @llvm.aarch64.neon.frecpx.f64(double) nounwind readnone
|
| D | fp16_intrinsic_scalar_1op.ll | 24 declare half @llvm.aarch64.neon.frecpx.f16(half)
344 ; CHECK: frecpx h0, h0
347 %vrecpxh_f16 = tail call half @llvm.aarch64.neon.frecpx.f16(half %a)
|
| D | sve-intrinsics-fp-arith.ll | 986 ; CHECK: frecpx z0.h, p0/m, z1.h
988 %out = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %a,
996 ; CHECK: frecpx z0.s, p0/m, z1.s
998 %out = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %a,
1006 ; CHECK: frecpx z0.d, p0/m, z1.d
1008 %out = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %a,
1623 declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>…
1624 declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i…
1625 declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x…
|
| D | f16-instructions.ll | 781 declare half @llvm.aarch64.neon.frecpx.f16(half %a) #0
1327 ; CHECK-FP16-NEXT: frecpx h0, h0
1331 %r = call half @llvm.aarch64.neon.frecpx.f16(half %a)
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 114 ;CHECK: frecpx s0, {{s[0-9]+}}
116 %tmp3 = call float @llvm.aarch64.neon.frecpx.f32(float %tmp1)
122 ;CHECK: frecpx d0, {{d[0-9]+}}
124 %tmp3 = call double @llvm.aarch64.neon.frecpx.f64(double %tmp1)
128 declare float @llvm.aarch64.neon.frecpx.f32(float) nounwind readnone
129 declare double @llvm.aarch64.neon.frecpx.f64(double) nounwind readnone
|
| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 492 __ frecpx(z7.VnH(), p6.Merging(), z7.VnH()); in TEST() local
964 __ frecpx(z9.VnS(), p0.Merging(), z14.VnS()); in TEST() local
1783 __ frecpx(z12.VnH(), p1.Merging(), z4.VnH()); in TEST() local
|
| D | test-disasm-sve-aarch64.cc | 1830 COMPARE_PREFIX(frecpx(z16.VnH(), p1.Merging(), z29.VnH()), in TEST()
1832 COMPARE_PREFIX(frecpx(z16.VnS(), p1.Merging(), z29.VnS()), in TEST()
1834 COMPARE_PREFIX(frecpx(z16.VnD(), p1.Merging(), z29.VnD()), in TEST()
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| D | test-cpu-features-aarch64.cc | 3330 TEST_FP_NEON(frecpx_0, frecpx(s0, s1))
3331 TEST_FP_NEON(frecpx_1, frecpx(d0, d1))
3707 TEST_FP_NEON_NEONHALF(frecpx_0, frecpx(h0, h1))
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| D | test-trace-aarch64.cc | 559 __ frecpx(d15, d18); in GenerateTestSequenceFP() local
560 __ frecpx(s5, s10); in GenerateTestSequenceFP() local
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 6238 LogicVRegister Simulator::frecpx(VectorFormat vform, in frecpx() function in vixl::aarch64::Simulator
6274 LogicVRegister Simulator::frecpx(VectorFormat vform, in frecpx() function in vixl::aarch64::Simulator
6278 frecpx<SimFloat16>(vform, dst, src); in frecpx()
6280 frecpx<float>(vform, dst, src); in frecpx()
6283 frecpx<double>(vform, dst, src); in frecpx()
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| D | simulator-aarch64.h | 4092 LogicVRegister frecpx(VectorFormat vform,
4095 LogicVRegister frecpx(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 2861 V(frecpx, Frecpx) \
4581 frecpx(zd, pg, zn); in Frecpx()
4586 frecpx(zd, pg.Merging(), zn); in Frecpx()
|
| D | assembler-aarch64.h | 2252 void frecpx(const VRegister& vd, const VRegister& vn);
4389 void frecpx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
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| D | simulator-aarch64.cc | 6508 frecpx(fpf, rd, rn); in VisitNEONScalar2RegMisc()
6601 frecpx(fpf, rd, rn); in VisitNEONScalar2RegMiscFP16()
8477 frecpx(vform, result, zn); in VisitSVEFPUnaryOp()
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1539 # CHECK: frecpx s18, s10
1540 # CHECK: frecpx d16, d19
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1539 # CHECK: frecpx s18, s10
1540 # CHECK: frecpx d16, d19
|