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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dfrintn.s10 frintn z31.h, p7/m, z31.h label
16 frintn z31.s, p7/m, z31.s label
22 frintn z31.d, p7/m, z31.d label
38 frintn z4.d, p7/m, z31.d label
50 frintn z4.d, p7/m, z31.d label
Dfrintn-diagnostics.s3 frintn z0.b, p0/m, z0.b label
8 frintn z0.s, p0/z, z0.s label
13 frintn z0.s, p8/m, z0.s label
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-simd-misc.s461 frintn v4.4h, v0.4h
462 frintn v6.8h, v8.8h
463 frintn v6.4s, v8.4s
464 frintn v6.2d, v8.2d
465 frintn v4.2s, v0.2s
Dfullfp16-neon-neg.s20 frintn.4h v0, v0
44 frintn.8h v0, v0
302 frintn v4.4h, v0.4h
304 frintn v6.8h, v8.8h
Darm64-fp-encoding.s652 frintn h1, h2
653 frintn s1, s2
654 frintn d1, d2 define
656 ; FP16: frintn h1, h2 ; encoding: [0x41,0x40,0xe4,0x1e]
658 ; NO-FP16-NEXT: frintn h1, h2
659 ; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e]
660 ; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e]
Darm64-advsimd.s581 frintn.2s v0, v0
631 ; CHECK: frintn.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x0e]
678 frintn.4h v0, v0
691 ; CHECK: frintn.4h v0, v0 ; encoding: [0x00,0x88,0x79,0x0e]
704 frintn.8h v0, v0
717 ; CHECK: frintn.8h v0, v0 ; encoding: [0x00,0x88,0x79,0x4e]
Dneon-diagnostics.s5796 frintn v0.16b, v31.16b
5797 frintn v2.8h, v4.8h
5798 frintn v1.8b, v9.8b
5799 frintn v13.4h, v21.4h
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s461 frintn v4.4h, v0.4h
462 frintn v6.8h, v8.8h
463 frintn v6.4s, v8.4s
464 frintn v6.2d, v8.2d
465 frintn v4.2s, v0.2s
Dfullfp16-neon-neg.s20 frintn.4h v0, v0
44 frintn.8h v0, v0
302 frintn v4.4h, v0.4h
304 frintn v6.8h, v8.8h
Darm64-fp-encoding.s652 frintn h1, h2
653 frintn s1, s2
654 frintn d1, d2 define
656 ; FP16: frintn h1, h2 ; encoding: [0x41,0x40,0xe4,0x1e]
658 ; NO-FP16-NEXT: frintn h1, h2
659 ; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e]
660 ; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e]
Darm64-advsimd.s581 frintn.2s v0, v0
631 ; CHECK: frintn.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x0e]
678 frintn.4h v0, v0
691 ; CHECK: frintn.4h v0, v0 ; encoding: [0x00,0x88,0x79,0x0e]
704 frintn.8h v0, v0
717 ; CHECK: frintn.8h v0, v0 ; encoding: [0x00,0x88,0x79,0x4e]
Dneon-diagnostics.s5856 frintn v0.16b, v31.16b
5857 frintn v2.8h, v4.8h
5858 frintn v1.8b, v9.8b
5859 frintn v13.4h, v21.4h
/external/vixl/test/aarch64/
Dtest-disasm-fp-aarch64.cc112 COMPARE(frintn(s10, s11), "frintn s10, s11"); in TEST()
113 COMPARE(frintn(s31, s30), "frintn s31, s30"); in TEST()
114 COMPARE(frintn(d12, d13), "frintn d12, d13"); in TEST()
115 COMPARE(frintn(d31, d30), "frintn d31, d30"); in TEST()
Dtest-api-movprfx-aarch64.cc504 __ frintn(z3.VnD(), p2.Merging(), z3.VnD()); in TEST() local
976 __ frintn(z7.VnH(), p6.Merging(), z11.VnH()); in TEST() local
1795 __ frintn(z25.VnH(), p4.Merging(), z1.VnH()); in TEST() local
Dtest-cpu-features-aarch64.cc641 TEST_FP(frintn_0, frintn(d0, d1))
642 TEST_FP(frintn_1, frintn(s0, s1))
3341 TEST_FP_NEON(frintn_0, frintn(v0.V2S(), v1.V2S()))
3342 TEST_FP_NEON(frintn_1, frintn(v0.V4S(), v1.V4S()))
3343 TEST_FP_NEON(frintn_2, frintn(v0.V2D(), v1.V2D()))
3502 TEST_FP_FPHALF(frintn_0, frintn(h0, h1))
3714 TEST_FP_NEON_NEONHALF(frintn_0, frintn(v0.V4H(), v1.V4H()))
3715 TEST_FP_NEON_NEONHALF(frintn_1, frintn(v0.V8H(), v1.V8H()))
/external/llvm/test/CodeGen/AArch64/
Darm64-vcvt.ll402 ;CHECK: frintn.2s v0, v0
404 %tmp3 = call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %A)
411 ;CHECK: frintn.4s v0, v0
413 %tmp3 = call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float> %A)
420 ;CHECK: frintn.2d v0, v0
422 %tmp3 = call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double> %A)
426 declare <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>) nounwind readnone
427 declare <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>) nounwind readnone
428 declare <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>) nounwind readnone
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs144 0x06,0x89,0x21,0x4e = frintn v6.4s, v8.4s
145 0x06,0x89,0x61,0x4e = frintn v6.2d, v8.2d
146 0x04,0x88,0x21,0x0e = frintn v4.2s, v0.2s
Dbasic-a64-instructions.s.cs709 0xac,0x41,0x24,0x1e = frintn s12, s13
722 0xac,0x41,0x64,0x1e = frintn d12, d13
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt285 # FP16: frintn h1, h2
286 # CHECK: frintn s1, s2
287 # CHECK: frintn d1, d2
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt285 # FP16: frintn h1, h2
286 # CHECK: frintn s1, s2
287 # CHECK: frintn d1, d2
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fp-rounding.ll320 ; CHECK-NEXT: frintn z0.h, p0/m, z0.h
330 ; CHECK-NEXT: frintn z0.h, p0/m, z0.h
340 ; CHECK-NEXT: frintn z0.h, p0/m, z0.h
350 ; CHECK-NEXT: frintn z0.s, p0/m, z0.s
360 ; CHECK-NEXT: frintn z0.s, p0/m, z0.s
370 ; CHECK-NEXT: frintn z0.d, p0/m, z0.d
Darm64-vcvt.ll591 ;CHECK: frintn.2s v0, v0
593 %tmp3 = call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %A)
600 ;CHECK: frintn.4s v0, v0
602 %tmp3 = call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float> %A)
609 ;CHECK: frintn.2d v0, v0
611 %tmp3 = call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double> %A)
615 declare <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>) nounwind readnone
616 declare <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>) nounwind readnone
617 declare <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>) nounwind readnone
Dsve-intrinsics-fp-arith.ll1122 ; CHECK: frintn z0.h, p0/m, z1.h
1124 %out = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %a,
1132 ; CHECK: frintn z0.s, p0/m, z1.s
1134 %out = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %a,
1142 ; CHECK: frintn z0.d, p0/m, z1.d
1144 %out = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %a,
1639 declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>…
1640 declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i…
1641 declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x…
/external/vixl/doc/
Dchangelog.md82 + Fixed simulation of `frintn` and `frinta` for corner cases.
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s605 frintn s12, s13 label
618 frintn d12, d13 label
1897 # CHECK-NEXT: 1 4 0.50 frintn s12, s13
1910 # CHECK-NEXT: 1 4 0.50 frintn d12, d13
3080 … - - - - 0.50 0.50 - - - - - - frintn s12, s13
3093 … - - - - 0.50 0.50 - - - - - - frintn d12, d13

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