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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dfrintp.s10 frintp z31.h, p7/m, z31.h label
16 frintp z31.s, p7/m, z31.s label
22 frintp z31.d, p7/m, z31.d label
38 frintp z4.d, p7/m, z31.d label
50 frintp z4.d, p7/m, z31.d label
Dfrintp-diagnostics.s3 frintp z0.b, p0/m, z0.b label
8 frintp z0.s, p0/z, z0.s label
13 frintp z0.s, p8/m, z0.s label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dinlineasm-illegal-type.ll10 %0 = tail call double asm "frintp ${0:d}, ${0:d}", "={d0}"()
16 %0 = tail call double asm "frintp ${0:d}, ${0:d}", "=w"()
Darm64-rounding.ll46 ; CHECK: frintp
57 ; CHECK: frintp
151 ; CHECK: frintp
160 ; CHECK: frintp
Darm64-vfloatintrinsics.ll173 ; CHECK-NOFP16-COUNT-4: frintp s{{[0-9]+}}, s{{[0-9]+}}
175 ; CHECK-FP16: frintp.4h
179 ; GISEL-NOFP16-COUNT-4: frintp s{{[0-9]+}}, s{{[0-9]+}}
181 ; GISEL-FP16: frintp.4h
430 ; CHECK-NOFP16-COUNT-8: frintp s{{[0-9]+}}, s{{[0-9]+}}
432 ; CHECK-FP16: frintp.8h
436 ; GISEL-NOFP16-COUNT-8: frintp s{{[0-9]+}}, s{{[0-9]+}}
438 ; GISEL-FP16: frintp.8h
651 ; CHECK: frintp.2s
652 ; GISEL: frintp.2s
[all …]
Dfloatdp_1source.ll46 ; CHECK: frintp {{s[0-9]+}}, {{s[0-9]+}}
85 ; CHECK: frintp {{d[0-9]+}}, {{d[0-9]+}}
Dsve-fixed-length-fp-rounding.ll30 ; CHECK: frintp v0.4h, v0.4h
39 ; CHECK: frintp v0.8h, v0.8h
49 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
62 ; VBITS_GE_512-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
71 ; VBITS_EQ_256-DAG: frintp [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h
72 ; VBITS_EQ_256-DAG: frintp [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h
86 ; VBITS_GE_1024-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
99 ; VBITS_GE_2048-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
111 ; CHECK: frintp v0.2s, v0.2s
120 ; CHECK: frintp v0.4s, v0.4s
[all …]
Dsve-fp-rounding.ll10 ; CHECK-NEXT: frintp z0.h, p0/m, z0.h
20 ; CHECK-NEXT: frintp z0.h, p0/m, z0.h
30 ; CHECK-NEXT: frintp z0.h, p0/m, z0.h
40 ; CHECK-NEXT: frintp z0.s, p0/m, z0.s
50 ; CHECK-NEXT: frintp z0.s, p0/m, z0.s
60 ; CHECK-NEXT: frintp z0.d, p0/m, z0.d
Dsve-intrinsics-fp-arith.ll1156 ; CHECK: frintp z0.h, p0/m, z1.h
1158 %out = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %a,
1166 ; CHECK: frintp z0.s, p0/m, z1.s
1168 %out = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %a,
1176 ; CHECK: frintp z0.d, p0/m, z1.d
1178 %out = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %a,
1643 declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>…
1644 declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i…
1645 declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x…
Darm64-vcvt.ll623 ;CHECK: frintp.2s v0, v0
633 ;CHECK: frintp.4s v0, v0
643 ;CHECK: frintp.2d v0, v0
Df16-instructions.ll1200 ; CHECK-CVT-NEXT: frintp [[INT32:s[0-9]+]], [[FLOAT32]]
1205 ; CHECK-FP16-NEXT: frintp h0, h0
1213 ; GISEL-CVT-NEXT: frintp [[INT32:s[0-9]+]], [[FLOAT32]]
1218 ; GISEL-FP16-NEXT: frintp h0, h0
/external/llvm/test/CodeGen/AArch64/
Darm64-rounding.ll46 ; CHECK: frintp
57 ; CHECK: frintp
151 ; CHECK: frintp
160 ; CHECK: frintp
Dfloatdp_1source.ll46 ; CHECK: frintp {{s[0-9]+}}, {{s[0-9]+}}
85 ; CHECK: frintp {{d[0-9]+}}, {{d[0-9]+}}
Darm64-vfloatintrinsics.ll86 ; CHECK: frintp.2s
210 ; CHECK: frintp.4s
334 ; CHECK: frintp.2d
Darm64-vcvt.ll433 ;CHECK: frintp.2s v0, v0
442 ;CHECK: frintp.4s v0, v0
451 ;CHECK: frintp.2d v0, v0
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-simd-misc.s485 frintp v4.4h, v0.4h
486 frintp v6.8h, v8.8h
487 frintp v6.4s, v8.4s
488 frintp v6.2d, v8.2d
489 frintp v4.2s, v0.2s
Dfullfp16-neon-neg.s22 frintp.4h v0, v0
46 frintp.8h v0, v0
310 frintp v4.4h, v0.4h
312 frintp v6.8h, v8.8h
Darm64-fp-encoding.s662 frintp h1, h2
663 frintp s1, s2
664 frintp d1, d2 define
666 ; FP16: frintp h1, h2 ; encoding: [0x41,0xc0,0xe4,0x1e]
668 ; NO-FP16-NEXT: frintp h1, h2
669 ; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e]
670 ; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e]
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s485 frintp v4.4h, v0.4h
486 frintp v6.8h, v8.8h
487 frintp v6.4s, v8.4s
488 frintp v6.2d, v8.2d
489 frintp v4.2s, v0.2s
Dfullfp16-neon-neg.s22 frintp.4h v0, v0
46 frintp.8h v0, v0
310 frintp v4.4h, v0.4h
312 frintp v6.8h, v8.8h
Darm64-fp-encoding.s662 frintp h1, h2
663 frintp s1, s2
664 frintp d1, d2 define
666 ; FP16: frintp h1, h2 ; encoding: [0x41,0xc0,0xe4,0x1e]
668 ; NO-FP16-NEXT: frintp h1, h2
669 ; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e]
670 ; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e]
Darm64-advsimd.s582 frintp.2s v0, v0
632 ; CHECK: frintp.2s v0, v0 ; encoding: [0x00,0x88,0xa1,0x0e]
679 frintp.4h v0, v0
692 ; CHECK: frintp.4h v0, v0 ; encoding: [0x00,0x88,0xf9,0x0e]
705 frintp.8h v0, v0
718 ; CHECK: frintp.8h v0, v0 ; encoding: [0x00,0x88,0xf9,0x4e]
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs150 0x06,0x89,0xa1,0x4e = frintp v6.4s, v8.4s
151 0x06,0x89,0xe1,0x4e = frintp v6.2d, v8.2d
152 0x04,0x88,0xa1,0x0e = frintp v4.2s, v0.2s
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt293 # FP16: frintp h1, h2
294 # CHECK: frintp s1, s2
295 # CHECK: frintp d1, d2
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt293 # FP16: frintp h1, h2
294 # CHECK: frintp s1, s2
295 # CHECK: frintp d1, d2

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