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Searched refs:g11 (Results 1 – 25 of 150) sorted by relevance

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/external/libopus/celt/
Dcelt.c99 opus_val16 g10, opus_val16 g11, opus_val16 g12) in comb_filter_const_c() argument
112 t = MAC16_32_Q16(t, g11, ADD32(x1,x3)); in comb_filter_const_c()
118 t = MAC16_32_Q16(t, g11, ADD32(x0,x2)); in comb_filter_const_c()
124 t = MAC16_32_Q16(t, g11, ADD32(x4,x1)); in comb_filter_const_c()
130 t = MAC16_32_Q16(t, g11, ADD32(x3,x0)); in comb_filter_const_c()
136 t = MAC16_32_Q16(t, g11, ADD32(x2,x4)); in comb_filter_const_c()
147 t = MAC16_32_Q16(t, g11, ADD32(x1,x3)); in comb_filter_const_c()
163 opus_val16 g10, opus_val16 g11, opus_val16 g12) in comb_filter_const_c() argument
176 + MULT16_32_Q15(g11,ADD32(x1,x3)) in comb_filter_const_c()
196 opus_val16 g00, g01, g02, g10, g11, g12; in comb_filter() local
[all …]
/external/mesa3d/src/intel/tools/tests/gen8/
Dcsel.asm1 csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
10 csel.l(16) g69<1>F -g11<4,4,1>F g11<4,4,1>F g67<4,4,1>F { align16 1H };
Dsel.asm7 (-f0.0) sel(16) g11<1>UD g58<8,8,1>UD 0x00000000UD { align1 1H };
16 (-f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q };
28 sel.l(8) g11<1>DF g35<4,4,1>DF g3<0,1,0>DF { align1 2Q };
29 (+f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q };
/external/libopus/celt/x86/
Dpitch_sse.h152 opus_val16 g11,
160 # define comb_filter_const(y, x, T, N, g10, g11, g12, arch) \ argument
161 ((void)(arch),comb_filter_const_sse(y, x, T, N, g10, g11, g12))
181 opus_val16 g11,
184 #define comb_filter_const(y, x, T, N, g10, g11, g12, arch) \ argument
185 ((*COMB_FILTER_CONST_IMPL[(arch) & OPUS_ARCHMASK])(y, x, T, N, g10, g11, g12))
/external/clang/test/Sema/
Dbitfield-layout.c225 struct g11 { struct
231 CHECK_SIZE(struct, g11, 24); argument
232 CHECK_ALIGN(struct, g11, 8);
233 CHECK_OFFSET(struct, g11, c, 16);
235 CHECK_SIZE(struct, g11, 16);
236 CHECK_ALIGN(struct, g11, 4);
237 CHECK_OFFSET(struct, g11, c, 12);
Dprivate-extern.c48 __private_extern__ int g11; in f5() local
49 __private_extern__ int g11; in f5() local
/external/llvm-project/clang/test/Sema/
Dbitfield-layout.c225 struct g11 { struct
231 CHECK_SIZE(struct, g11, 24); argument
232 CHECK_ALIGN(struct, g11, 8);
233 CHECK_OFFSET(struct, g11, c, 16);
235 CHECK_SIZE(struct, g11, 16);
236 CHECK_ALIGN(struct, g11, 4);
237 CHECK_OFFSET(struct, g11, c, 12);
Dprivate-extern.c48 __private_extern__ int g11; in f5() local
49 __private_extern__ int g11; in f5() local
/external/mesa3d/src/intel/tools/tests/gen7/
Dadd.asm3 add(1) g11.4<1>UD g11<0,1,0>UD 0x00000001UD { align1 1N };
5 add(1) a0<1>UW g11<0,1,0>UW 0x0008UW { align1 WE_all 1N };
7 add(16) g19<1>F g11<8,8,1>F -g6.4<0,1,0>F { align1 1H };
23 add(8) g11<1>F g10<4>.xF 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q …
38 add(16) g11<1>UD g9<8,8,1>D 0x00000001UD { align1 1H };
43 add(8) g13<1>UD g11<8,8,1>UD 1D { align1 1Q };
Dmad.asm1 mad(8) g11<1>F g4.7<0,1,0>F g4.3<0,1,0>F g9<4,4,1>F { align16 1Q };
3 mad(8) g18<1>.xyzF -g16<4,4,1>.xyzzF g11<4,4,1>.xyzzF g9<4,4,1>.xyzzF { align16 1Q };
21 mad(8) g125<1>F g11<4,4,1>F -g13.0<0,1,0>F g6<4,4,1>F { align16 1Q };
22 mad(8) g123<1>F g2<4,4,1>F -g64.0<0,1,0>F g11<4,4,1>F { align16 2Q };
25 mad(8) g11<1>.yF -g27<4,4,1>.xF g7.2<0,1,0>F g6.0<0,1,0>F { align16 NoDDClr,NoDD…
Ddp3.asm1 dp3(8) g12<1>.xF g11<4>.xyzzF g11<4>.xyzzF { align16 1Q };
Dshr.asm1 shr(1) g11<1>UD g11<0,1,0>UD 0x0000000fUD { align1 1N };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dmov.asm29 mov.z.f0.0(8) null<1>F g11<0>.xUD { align16 1Q };
80 mov(8) g11<1>UD 0D { align1 WE_all 1Q };
81 mov(1) g11.7<1>UD 65535D { align1 WE_all 1N };
82 mov(8) g11<1>UD 0D { align1 WE_all 2Q };
84 mov(1) g11.7<1>UD 65535D { align1 WE_all 3N };
90 mov(8) g19<1>.xUD g11<4>.xD { align16 1Q };
94 mov(8) g11<1>UD g9<16,8,2>UW { align1 1Q };
95 mov(16) g15<1>UD g11<8,8,1>F { align1 1H };
120 mov(8) g10<1>D g11<8,4,2>UD { align1 2Q };
134 mov(8) g11<1>D 0D { align1 2Q };
[all …]
Dadd.asm5 add(1) g11.4<1>UD g11<0,1,0>UD 0x00000001UD { align1 1N };
7 add(1) a0<1>UW g11<0,1,0>UW 0x0008UW { align1 WE_all 1N };
15 add(8) g11<1>.xD g5<4>.xD 64D { align16 1Q };
28 add(8) g11<1>F g10<4>.xF 0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q …
45 add(16) g11<1>UD g9<8,8,1>D 0x00000001UD { align1 1H };
52 add(8) g13<1>UD g11<8,8,1>UD 1D { align1 1Q };
Ddp3.asm1 dp3(8) g12<1>.xF g11<4>.xyzzF g11<4>.xyzzF { align16 1Q };
Dshr.asm1 shr(1) g11<1>UD g11<0,1,0>UD 0x00000010UD { align1 1N };
Dpln.asm6 pln.g.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H };
8 pln.l.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H };
/external/mesa3d/src/intel/tools/tests/gen6/
Dshl.asm4 shl(8) g11<1>D g11<4>D 16D { align16 1Q };
13 shl(16) g13<1>D g2.5<0,1,0>D g11<8,8,1>UD { align1 1H };
Dmul.asm19 mul.sat(16) g13<1>F g11<8,8,1>F 0x40a00001F /* 5F */ { align1 1H };
37 mul(8) m3<1>.xyzF g2<4>.xyzzF g11<4>.xF { align16 NoDDClr 1Q };
54 mul(8) acc0<1>UD g9<4>UD g11<4>UD { align16 1Q };
57 mul(8) g3<1>.wF g1<0>.zF g11<4>.xF { align16 NoDDClr,NoDDChk 1Q };
58 mul(8) m4<1>.yF g15<4>.xF g11<4>.xF { align16 NoDDClr,NoDDChk 1Q };
59 mul(8) m5<1>.yF g31<4>.xF g11<4>.xF { align16 NoDDChk 1Q };
Dmov.asm22 mov(8) m2<1>D g11<8,8,1>F { align1 1Q };
42 mov(8) g21<1>F g11<8,8,1>F { align1 2Q };
69 mov(8) g12<1>F g11<4>D { align16 1Q };
76 mov(8) g11<1>UD g11<4>F { align16 1Q };
77 mov(8) g12<1>F g11<4>UD { align16 1Q };
91 mov(8) g3<1>D g11<4>D { align16 1Q };
153 mov.sat(8) m4<1>.yF -g11<4>.xD { align16 NoDDClr,NoDDChk 1Q };
156 mov(16) m1<1>UD g11<8,8,1>F { align1 1H };
163 mov.nz.f0.0(8) g11<1>F -(abs)g1<0>F { align16 1Q };
164 (+f0.0) mov(8) g11<1>F 0xbf800000F /* -1F */ { align16 1Q };
Dasr.asm1 asr(8) g11<1>D g11<4>D 16D { align16 1Q };
/external/libopus/celt/mips/
Dcelt_mipsr1.h68 opus_val16 g00, g01, g02, g10, g11, g12; in comb_filter() local
86 g11 = MULT16_16_P15(g1, gains[tapset1][1]); in comb_filter()
108 … asm volatile("MADD $ac1, %0, %1" : : "r" ((int)MULT16_16_Q15(f,g11)), "r" ((int)ADD32(x3,x1))); in comb_filter()
141 asm volatile("MADD $ac1, %0, %1" : : "r" ((int)g11), "r" ((int)ADD32(x3,x1))); in comb_filter()
/external/mesa3d/src/intel/tools/tests/gen9/
Dcsel.asm1 csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dshl.asm4 shl(8) g11<1>.xUD g11<4>.xUD 4D { align16 };
/external/mesa3d/src/intel/tools/tests/gen5/
Dshl.asm4 shl(8) g11<1>.xUD g11<4>.xUD 4D { align16 };

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