/external/clang/test/Sema/ |
D | bitfield-layout.c | 268 struct __attribute__((packed)) g14 { struct 274 CHECK_SIZE(struct, g14, 16); argument 275 CHECK_ALIGN(struct, g14, 8); 276 CHECK_OFFSET(struct, g14, c, 8); 278 CHECK_SIZE(struct, g14, 9); 279 CHECK_ALIGN(struct, g14, 1); 280 CHECK_OFFSET(struct, g14, c, 8); 282 CHECK_SIZE(struct, g14, 5); 283 CHECK_ALIGN(struct, g14, 1); 284 CHECK_OFFSET(struct, g14, c, 4);
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D | private-extern.c | 66 extern struct s0 g14; in f8() 67 __private_extern__ struct s0 g14; in f8() local
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/external/llvm-project/clang/test/Sema/ |
D | bitfield-layout.c | 268 struct __attribute__((packed)) g14 { struct 274 CHECK_SIZE(struct, g14, 16); argument 275 CHECK_ALIGN(struct, g14, 8); 276 CHECK_OFFSET(struct, g14, c, 8); 278 CHECK_SIZE(struct, g14, 9); 279 CHECK_ALIGN(struct, g14, 1); 280 CHECK_OFFSET(struct, g14, c, 8); 282 CHECK_SIZE(struct, g14, 5); 283 CHECK_ALIGN(struct, g14, 1); 284 CHECK_OFFSET(struct, g14, c, 4);
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D | private-extern.c | 66 extern struct s0 g14; in f8() 67 __private_extern__ struct s0 g14; in f8() local
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/external/mesa3d/src/intel/tools/tests/gen6/ |
D | mul.asm | 2 mul(16) m5<1>F g2<8,8,1>F g14<8,8,1>F { align1 1H }; 22 mul(8) g14<1>D g14<8,8,1>D g13<8,8,1>D { align1 1Q }; 23 mul(16) acc0<1>UD g14<8,8,1>UD 0xaaaaaaabUD { align1 1H }; 24 mul(16) acc0<1>D g14<8,8,1>D 1431655766D { align1 1H }; 31 mul.l.f0.0(16) g14<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1H }; 61 mul(16) m17<1>D g16<8,8,1>D g14<8,8,1>D { align1 1H };
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D | mach.asm | 3 mach(16) g17<1>UD g14<8,8,1>UD 0xaaaaaaabUD { align1 1H AccWrEnable }; 4 mach(16) g25<1>D g14<8,8,1>D 1431655766D { align1 1H AccWrEnable };
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D | mad.asm | 17 mad(8) g2<1>F -g22<4,4,1>F g14<4,4,1>F -g14<4,4,1>F { align16 2Q }; 18 mad(8) g43<1>F -g20<4,4,1>F -g12.1<0,1,0>F -g14<4,4,1>F { align16 2Q }; 19 mad.sat(8) g12<1>F g4<4,4,1>F g68<4,4,1>F g14<4,4,1>F { align16 2Q };
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D | sel.asm | 24 (+f0.0.any4h) sel(8) g15<1>UD g14<4>UD g4<4>UD { align16 1Q }; 39 sel.l(16) g20<1>F g14<8,8,1>F 0x40400000F /* 3F */ { align1 1H }; 41 (-f0.0) sel(8) g15<1>F (abs)g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; 52 sel.l(16) m1<1>F g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1H };
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/external/mesa3d/src/intel/tools/tests/gen7/ |
D | math.asm | 7 math pow(8) g20<1>F g14<8,8,1>F g20<0,1,0>F { align1 1Q }; 10 math pow(8) g14<1>.xF g13<4>.xF g12<4>.xF { align16 1Q }; 13 math cos(8) g5<1>.yF g14<4>.xF null<4>F { align16 1Q }; 16 math log(8) g15<1>.xF g14<4>.xF null<4>F { align16 1Q }; 20 math intdiv(8) g14<1>.xyzUD g6<0>.xyzzUD g6.4<0>.xyzzUD { align16 1Q };
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D | sel.asm | 16 (-f0.0.z) sel(8) g3<1>.zUD g14<4>.xUD 0x00000000UD { align16 1Q }; 17 sel.l(8) g14<1>UD g6<0>UD g6.4<0>UD { align16 1Q }; 34 sel.l(8) g14<1>.xD g12<4>.xD 1D { align16 1Q }; 52 (-f0.0) sel(16) g55<1>F (abs)g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1H };
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/external/mesa3d/src/intel/tools/tests/gen7.5/ |
D | math.asm | 8 math pow(8) g20<1>F g14<8,8,1>F g20<0,1,0>F { align1 1Q }; 12 math pow(8) g14<1>.xF g13<4>.xF g12<4>.xF { align16 1Q }; 17 math cos(8) g5<1>.yF g14<4>.xF null<4>F { align16 1Q }; 20 math log(8) g15<1>.xF g14<4>.xF null<4>F { align16 1Q }; 26 math intdiv(8) g14<1>.xyzUD g6<0>.xyzzUD g6.4<0>.xyzzUD { align16 1Q };
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D | sel.asm | 21 sel.l(8) g86<1>UD g14<4>.xUD 0x0fffffffUD { align16 1Q }; 24 (-f0.0.z) sel(8) g3<1>.zUD g14<4>.xUD 0x00000000UD { align16 1Q }; 25 sel.l(8) g14<1>UD g6<0>UD g6.4<0>UD { align16 1Q }; 53 sel.l(8) g14<1>.xD g12<4>.xD 1D { align16 1Q }; 59 (-f0.0) sel(8) g15<1>F (abs)g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q };
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D | mach.asm | 9 mach(8) g15<1>D g12<4>D g14<4>D { align16 1Q AccWrEnable }; 14 mach(8) g22<1>D g6<8,8,1>D g14<8,8,1>D { align1 2Q AccWrEnable };
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D | shl.asm | 11 shl(8) g14<1>.xUD g12<4>.yUD 0x00000010UD { align16 1Q }; 12 shl(8) g16<1>.xUD g15<4>.xUD g14<4>.xUD { align16 WE_all 1Q };
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/external/igt-gpu-tools/assembler/doc/examples/ |
D | packed_yuv_wm.g4a | 100 * Y is g14, g15. 109 add (8) g14<1>F g14<8,8,1>F -0.0627451F { align1 }; 115 mul (8) g14<1>F g14<8,8,1>F 1.164F { align1 }; 119 mac.sat (8) m2<1>F g14<8,8,1>F 1F { align1 }; 125 mac.sat (8) m3<1>F g14<8,8,1>F 1F { align1 }; 129 mac.sat (8) m4<1>F g14<8,8,1>F 1F { align1 };
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/external/mesa3d/src/intel/tools/tests/gen4.5/ |
D | or.asm | 1 or(8) g13<1>.xUD g13<4>.xUD g14<4>.xUD { align16 }; 3 or(16) g12<1>UD g14<8,8,1>UD g20<8,8,1>UD { align1 compr };
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D | mul.asm | 11 mul.sat(16) m2<1>F g14<8,8,1>F g6<8,8,1>F { align1 compr }; 15 mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr }; 26 mul.l.f0.0(16) g14<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr };
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/external/mesa3d/src/intel/tools/tests/gen4/ |
D | or.asm | 2 or(8) g13<1>.xUD g13<4>.xUD g14<4>.xUD { align16 }; 4 or(16) g12<1>UD g14<8,8,1>UD g20<8,8,1>UD { align1 compr };
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D | mul.asm | 1 mul(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr }; 14 mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr }; 27 mul.l.f0.0(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr };
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/external/mesa3d/src/intel/tools/tests/gen9/ |
D | or.asm | 16 or(16) g16<1>UW g14<16,16,1>UW g15<16,16,1>UW { align1 1H }; 21 or(1) g14<1>UD g14<0,1,0>UD g19<0,1,0>UD { align1 WE_all 3N };
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/external/mesa3d/src/intel/tools/tests/gen8/ |
D | mul.asm | 15 mul.sat(16) g16<1>F g10<8,8,1>F g14<8,8,1>F { align1 1H }; 25 mul(8) g21<1>Q g6<4,4,1>D g14<4,4,1>D { align1 2Q }; 28 mul(16) g15<1>UW g14<16,16,1>UW 0x0808UW { align1 1H };
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/external/mesa3d/src/intel/tools/tests/gen5/ |
D | and.asm | 4 and(16) g14<1>D g12<8,8,1>D 1D { align1 compr }; 18 and.nz.f0.0(16) g14<1>D g8<8,8,1>D 1D { align1 compr };
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D | add.asm | 10 add(8) g14<1>F g6<8,8,1>F 0x3f800000F /* 1F */ { align1 }; 13 add(16) g14<1>D g14<8,8,1>D 1D { align1 compr };
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc64-fastcc.ll | 7 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 15 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 23 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 31 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 39 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 47 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 55 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 63 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 71 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 79 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … [all …]
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/external/llvm-project/llvm/test/CodeGen/PowerPC/ |
D | ppc64-fastcc.ll | 7 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 15 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 23 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 31 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 39 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 47 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 55 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 63 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 71 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … 79 …, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x … [all …]
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