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/external/mesa3d/src/intel/tools/tests/gen4/
Dmul.asm1 mul(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr };
7 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
10 mul.sat(16) m2<1>F g16<8,8,1>F g6<8,8,1>F { align1 compr };
14 mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr };
27 mul.l.f0.0(16) g16<1>F g14<8,8,1>F g12<8,8,1>F { align1 compr };
28 mul.nz.f0.0(16) g18<1>F g16<8,8,1>F g12<8,8,1>F { align1 compr };
/external/mesa3d/src/intel/tools/tests/gen7/
Dadd.asm31 (+f0.0) add(8) g16<1>D -g16<4>D 31D { align16 1Q };
34 add(8) g4.1<2>UW g4.1<16,8,2>UW g16<16,8,2>UW { align1 1Q };
44 add(16) g19<1>UD g16<8,8,1>UD 1D { align1 1H };
54 add(8) g18<1>F -g16<4>.xyxyF g16<4>.zwzwF { align16 2Q };
Dmad.asm3 mad(8) g18<1>.xyzF -g16<4,4,1>.xyzzF g11<4,4,1>.xyzzF g9<4,4,1>.xyzzF { align16 1Q };
36 mad(8) g5<1>.xF -g16<4,4,1>.xF g2.2<0,1,0>F g1.5<0,1,0>F { align16 NoDDClr 1Q };
38 mad.nz.f0.0(8) g16<1>F -g33.0<0,1,0>F g10<4,4,1>F g18<4,4,1>F { align16 2Q };
Dfbh.asm1 fbh(8) g16<1>D g15<4>D { align16 1Q };
Dbfi1.asm3 bfi1(16) g16<1>UD g14<8,8,1>D g12<8,8,1>D { align1 1H };
/external/mesa3d/src/intel/tools/tests/gen6/
Dor.asm5 or(16) g16<1>UD g14<8,8,1>UD g12<8,8,1>UD { align1 1H };
7 or.nz.f0.0(8) null<1>.xUD g17<4>.xUD g16<4>.xUD { align16 1Q };
8 or.nz.f0.0(8) null<1>UD g16<8,8,1>UD g17<8,8,1>UD { align1 1Q };
Dmath.asm3 math pow(8) g16<1>F g15<8,8,1>F g14<8,8,1>F { align1 1Q };
7 math sqrt(8) g16<1>F g15<8,8,1>F null<8,8,1>F { align1 1Q };
Dlzd.asm1 lzd(8) g16<1>UD g17<4>UD { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen8/
Dlrp.asm1 lrp(8) g4<1>F g16<4,4,1>F g7.2<0,1,0>F g6.6<0,1,0>F { align16 1Q };
4 lrp.sat(8) g7<1>F g10<4,4,1>F g13<4,4,1>F g16<4,4,1>F { align16 1Q };
Dmul.asm14 mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q };
15 mul.sat(16) g16<1>F g10<8,8,1>F g14<8,8,1>F { align1 1H };
21 mul.sat(8) g10<1>DF g10<4,4,1>DF g16<4,4,1>DF { align1 2Q };
Dbfi1.asm2 bfi1(16) g16<1>UD g14<8,8,1>D g12<8,8,1>D { align1 1H };
/external/mesa3d/src/intel/tools/tests/gen9/
Dlrp.asm1 lrp(8) g4<1>F g16<4,4,1>F g7.2<0,1,0>F g6.6<0,1,0>F { align16 1Q };
4 lrp.sat(8) g7<1>F g10<4,4,1>F g13<4,4,1>F g16<4,4,1>F { align16 1Q };
Dbfi1.asm2 bfi1(16) g16<1>UD g14<8,8,1>D g12<8,8,1>D { align1 1H };
Dmul.asm14 mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q };
21 mul.sat(8) g10<1>DF g10<4,4,1>DF g16<4,4,1>DF { align1 2Q };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dor.asm20 or(1) g113.21<1>UB g16<0,1,0>UB g16.16<0,1,0>UB { align1 WE_all 1N };
22 or(16) g16<1>UW g14<16,16,1>UW g15<16,16,1>UW { align1 1H };
Dadd.asm34 (+f0.0) add(8) g16<1>D -g16<4>D 31D { align16 1Q };
35 add(8) g18<1>.xUD g16<4>.xUD 0xffffffffUD { align16 1Q };
40 add(8) g16<1>UD g29<0,1,0>UD g26<1,4,0>UW { align1 1Q };
53 add(16) g19<1>UD g16<8,8,1>UD 1D { align1 1H };
Dfbh.asm1 fbh(8) g16<1>D g15<4>D { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen5/
Dmul.asm10 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
17 mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr };
22 mul(16) g4<1>D g16<8,8,1>D g8<8,8,1>D { align1 compr };
Dsel.asm8 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
16 (+f0.0) sel(8) g15<1>UD g16<4>UD g15<4>UD { align16 };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dmul.asm7 mul(16) g22<1>F g16<8,8,1>F 0x41800000F /* 16F */ { align1 compr };
15 mul.sat(16) g18<1>F g16<8,8,1>F g14<8,8,1>F { align1 compr };
28 mul.nz.f0.0(16) g16<1>F g10<8,8,1>F g12<8,8,1>F { align1 compr };
/external/llvm-project/llvm/test/CodeGen/X86/
Dfold-rmw-ops.ll8 @g16 = external dso_local global i16, align 2
379 ; CHECK-NEXT: # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
392 %load1 = load i16, i16* @g16
395 store i16 %add, i16* @g16
412 ; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
424 %load1 = load i16, i16* @g16
426 store i16 %add, i16* @g16
443 ; CHECK-NEXT: # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
455 %load1 = load i16, i16* @g16
457 store i16 %add, i16* @g16
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
15 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
23 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
31 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
39 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
47 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
55 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
63 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
71 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
79 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
15 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
23 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
31 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
39 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
47 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
55 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
63 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
71 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
79 …, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x …
[all …]
/external/igt-gpu-tools/assembler/doc/examples/
Dpacked_yuv_wm.g4a102 * Cb is g16, g17.
113 add (8) g16<1>F g16<8,8,1>F -0.501961F { align1 };
123 mac (8) null g16<8,8,1>F -0.392F { align1 };
127 mul (8) null g16<8,8,1>F 2.017F { align1 };
/external/libwebsockets/lib/misc/fts/
Dtrie.c193 g16(unsigned char *b, int d) in g16() function
403 bp += g16(&buf[bp], 0); in finalize_per_input()
404 bp += g16(&buf[bp], 0); in finalize_per_input()
572 bp += g16(&linetable[bp], 0); in lws_fts_fill()
573 bp += g16(&linetable[bp], 0); in lws_fts_fill()
1065 g16(linetable, t->c - lbh); in lws_fts_fill()
1066 g16(linetable + 2, t->line_number - sline); in lws_fts_fill()

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