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Searched refs:ge (Results 1 – 25 of 803) sorted by relevance

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/external/llvm/test/MC/ARM/
Dv8_IT_manual.s5 it ge
9 it ge
12 it ge
15 it ge
19 it ge
23 it ge
27 it ge
31 it ge
35 it ge
39 it ge
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dv8_IT_manual.s5 it ge
9 it ge
12 it ge
15 it ge
19 it ge
23 it ge
27 it ge
31 it ge
35 it ge
39 it ge
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc116 {{ge, r1, 250}, true, ge, "ge r1 250", "ge_r1_250"},
125 {{ge, r6, 203}, true, ge, "ge r6 203", "ge_r6_203"},
132 {{ge, r4, 133}, true, ge, "ge r4 133", "ge_r4_133"},
151 {{ge, r7, 217}, true, ge, "ge r7 217", "ge_r7_217"},
158 {{ge, r1, 182}, true, ge, "ge r1 182", "ge_r1_182"},
169 {{ge, r5, 91}, true, ge, "ge r5 91", "ge_r5_91"},
177 {{ge, r0, 171}, true, ge, "ge r0 171", "ge_r0_171"},
179 {{ge, r5, 245}, true, ge, "ge r5 245", "ge_r5_245"},
183 {{ge, r1, 17}, true, ge, "ge r1 17", "ge_r1_17"},
195 {{ge, r0, 210}, true, ge, "ge r0 210", "ge_r0_210"},
[all …]
Dtest-assembler-cond-rd-operand-rn-in-it-block-t32.cc2346 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"},
2347 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"},
2348 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"},
2349 {{ge, r0, r3}, true, ge, "ge r0 r3", "ge_r0_r3"},
2350 {{ge, r0, r4}, true, ge, "ge r0 r4", "ge_r0_r4"},
2351 {{ge, r0, r5}, true, ge, "ge r0 r5", "ge_r0_r5"},
2352 {{ge, r0, r6}, true, ge, "ge r0 r6", "ge_r0_r6"},
2353 {{ge, r0, r7}, true, ge, "ge r0 r7", "ge_r0_r7"},
2354 {{ge, r0, r8}, true, ge, "ge r0 r8", "ge_r0_r8"},
2355 {{ge, r0, r9}, true, ge, "ge r0 r9", "ge_r0_r9"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc735 {{ge, r0, r0, 0}, true, ge, "ge r0 r0 0", "ge_r0_r0_0"},
736 {{ge, r0, r1, 0}, true, ge, "ge r0 r1 0", "ge_r0_r1_0"},
737 {{ge, r0, r2, 0}, true, ge, "ge r0 r2 0", "ge_r0_r2_0"},
738 {{ge, r0, r3, 0}, true, ge, "ge r0 r3 0", "ge_r0_r3_0"},
739 {{ge, r0, r4, 0}, true, ge, "ge r0 r4 0", "ge_r0_r4_0"},
740 {{ge, r0, r5, 0}, true, ge, "ge r0 r5 0", "ge_r0_r5_0"},
741 {{ge, r0, r6, 0}, true, ge, "ge r0 r6 0", "ge_r0_r6_0"},
742 {{ge, r0, r7, 0}, true, ge, "ge r0 r7 0", "ge_r0_r7_0"},
743 {{ge, r1, r0, 0}, true, ge, "ge r1 r0 0", "ge_r1_r0_0"},
744 {{ge, r1, r1, 0}, true, ge, "ge r1 r1 0", "ge_r1_r1_0"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc735 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"},
736 {{ge, r0, r1}, true, ge, "ge r0 r1", "ge_r0_r1"},
737 {{ge, r0, r2}, true, ge, "ge r0 r2", "ge_r0_r2"},
738 {{ge, r0, r3}, true, ge, "ge r0 r3", "ge_r0_r3"},
739 {{ge, r0, r4}, true, ge, "ge r0 r4", "ge_r0_r4"},
740 {{ge, r0, r5}, true, ge, "ge r0 r5", "ge_r0_r5"},
741 {{ge, r0, r6}, true, ge, "ge r0 r6", "ge_r0_r6"},
742 {{ge, r0, r7}, true, ge, "ge r0 r7", "ge_r0_r7"},
743 {{ge, r1, r0}, true, ge, "ge r1 r0", "ge_r1_r0"},
744 {{ge, r1, r1}, true, ge, "ge r1 r1", "ge_r1_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"},
118 {{ge, r7, r1, 0}, true, ge, "ge r7 r1 0", "ge_r7_r1_0"},
119 {{ge, r2, r0, 0}, true, ge, "ge r2 r0 0", "ge_r2_r0_0"},
120 {{ge, r1, r7, 0}, true, ge, "ge r1 r7 0", "ge_r1_r7_0"},
143 {{ge, r0, r5, 3}, true, ge, "ge r0 r5 3", "ge_r0_r5_3"},
148 {{ge, r0, r0, 6}, true, ge, "ge r0 r0 6", "ge_r0_r0_6"},
169 {{ge, r0, r3, 2}, true, ge, "ge r0 r3 2", "ge_r0_r3_2"},
171 {{ge, r7, r3, 5}, true, ge, "ge r7 r3 5", "ge_r7_r3_5"},
199 {{ge, r2, r3, 5}, true, ge, "ge r2 r3 5", "ge_r2_r3_5"},
211 {{ge, r2, r4, 0}, true, ge, "ge r2 r4 0", "ge_r2_r4_0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc735 {{ge, r0, r0, r0}, true, ge, "ge r0 r0 r0", "ge_r0_r0_r0"},
736 {{ge, r0, r1, r0}, true, ge, "ge r0 r1 r0", "ge_r0_r1_r0"},
737 {{ge, r0, r2, r0}, true, ge, "ge r0 r2 r0", "ge_r0_r2_r0"},
738 {{ge, r0, r3, r0}, true, ge, "ge r0 r3 r0", "ge_r0_r3_r0"},
739 {{ge, r0, r4, r0}, true, ge, "ge r0 r4 r0", "ge_r0_r4_r0"},
740 {{ge, r0, r5, r0}, true, ge, "ge r0 r5 r0", "ge_r0_r5_r0"},
741 {{ge, r0, r6, r0}, true, ge, "ge r0 r6 r0", "ge_r0_r6_r0"},
742 {{ge, r0, r7, r0}, true, ge, "ge r0 r7 r0", "ge_r0_r7_r0"},
743 {{ge, r1, r0, r1}, true, ge, "ge r1 r0 r1", "ge_r1_r0_r1"},
744 {{ge, r1, r1, r1}, true, ge, "ge r1 r1 r1", "ge_r1_r1_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
103 {{ge, r4, r4, 195}, true, ge, "ge r4 r4 195", "ge_r4_r4_195"},
124 {{ge, r6, r6, 88}, true, ge, "ge r6 r6 88", "ge_r6_r6_88"},
126 {{ge, r5, r5, 242}, true, ge, "ge r5 r5 242", "ge_r5_r5_242"},
154 {{ge, r1, r1, 103}, true, ge, "ge r1 r1 103", "ge_r1_r1_103"},
157 {{ge, r7, r7, 22}, true, ge, "ge r7 r7 22", "ge_r7_r7_22"},
187 {{ge, r1, r1, 69}, true, ge, "ge r1 r1 69", "ge_r1_r1_69"},
279 {{ge, r0, r0, 223}, true, ge, "ge r0 r0 223", "ge_r0_r0_223"},
295 {{ge, r4, r4, 208}, true, ge, "ge r4 r4 208", "ge_r4_r4_208"},
303 {{ge, r7, r7, 233}, true, ge, "ge r7 r7 233", "ge_r7_r7_233"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
135 {{ge, r3, r3, r7}, true, ge, "ge r3 r3 r7", "ge_r3_r3_r7"},
152 {{ge, r2, r2, r5}, true, ge, "ge r2 r2 r5", "ge_r2_r2_r5"},
209 {{ge, r2, r2, r6}, true, ge, "ge r2 r2 r6", "ge_r2_r2_r6"},
227 {{ge, r6, r6, r4}, true, ge, "ge r6 r6 r4", "ge_r6_r6_r4"},
242 {{ge, r3, r3, r6}, true, ge, "ge r3 r3 r6", "ge_r3_r3_r6"},
257 {{ge, r4, r4, r6}, true, ge, "ge r4 r4 r6", "ge_r4_r4_r6"},
265 {{ge, r0, r0, r6}, true, ge, "ge r0 r0 r6", "ge_r0_r0_r6"},
277 {{ge, r2, r2, r2}, true, ge, "ge r2 r2 r2", "ge_r2_r2_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc124 {{ge, r1, r3, r4}, true, ge, "ge r1 r3 r4", "ge_r1_r3_r4"},
127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"},
129 {{ge, r7, r2, r4}, true, ge, "ge r7 r2 r4", "ge_r7_r2_r4"},
132 {{ge, r0, r7, r7}, true, ge, "ge r0 r7 r7", "ge_r0_r7_r7"},
140 {{ge, r6, r5, r5}, true, ge, "ge r6 r5 r5", "ge_r6_r5_r5"},
168 {{ge, r3, r2, r3}, true, ge, "ge r3 r2 r3", "ge_r3_r2_r3"},
181 {{ge, r4, r3, r6}, true, ge, "ge r4 r3 r6", "ge_r4_r3_r6"},
183 {{ge, r6, r7, r6}, true, ge, "ge r6 r7 r6", "ge_r6_r7_r6"},
185 {{ge, r4, r2, r3}, true, ge, "ge r4 r2 r3", "ge_r4_r2_r3"},
186 {{ge, r3, r5, r1}, true, ge, "ge r3 r5 r1", "ge_r3_r5_r1"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
127 {{ge, r4, r4, LSL, r0}, true, ge, "ge r4 r4 LSL r0", "ge_r4_r4_LSL_r0"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
156 {{ge, r3, r3, ROR, r7}, true, ge, "ge r3 r3 ROR r7", "ge_r3_r3_ROR_r7"},
162 {{ge, r4, r4, ROR, r1}, true, ge, "ge r4 r4 ROR r1", "ge_r4_r4_ROR_r1"},
165 {{ge, r3, r3, LSL, r4}, true, ge, "ge r3 r3 LSL r4", "ge_r3_r3_LSL_r4"},
170 {{ge, r1, r1, ASR, r2}, true, ge, "ge r1 r1 ASR r2", "ge_r1_r1_ASR_r2"},
171 {{ge, r7, r7, LSR, r4}, true, ge, "ge r7 r7 LSR r4", "ge_r7_r7_LSR_r4"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
105 {{ge, r0, r1, LSL, 6}, true, ge, "ge r0 r1 LSL 6", "ge_r0_r1_LSL_6"},
126 {{ge, r1, r3, LSL, 10}, true, ge, "ge r1 r3 LSL 10", "ge_r1_r3_LSL_10"},
143 {{ge, r5, r3, LSL, 26}, true, ge, "ge r5 r3 LSL 26", "ge_r5_r3_LSL_26"},
147 {{ge, r1, r3, LSL, 20}, true, ge, "ge r1 r3 LSL 20", "ge_r1_r3_LSL_20"},
165 {{ge, r1, r3, LSL, 25}, true, ge, "ge r1 r3 LSL 25", "ge_r1_r3_LSL_25"},
168 {{ge, r4, r5, LSL, 19}, true, ge, "ge r4 r5 LSL 19", "ge_r4_r5_LSL_19"},
181 {{ge, r2, r3, LSL, 21}, true, ge, "ge r2 r3 LSL 21", "ge_r2_r3_LSL_21"},
241 {{ge, r2, r0, LSL, 4}, true, ge, "ge r2 r0 LSL 4", "ge_r2_r0_LSL_4"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc107 {{ge, r7, r7, r12}, true, ge, "ge r7 r7 r12", "ge_r7_r7_r12"},
116 {{ge, r12, r12, r2}, true, ge, "ge r12 r12 r2", "ge_r12_r12_r2"},
120 {{ge, r14, r14, r4}, true, ge, "ge r14 r14 r4", "ge_r14_r14_r4"},
125 {{ge, r3, r3, r12}, true, ge, "ge r3 r3 r12", "ge_r3_r3_r12"},
203 {{ge, r5, r5, r6}, true, ge, "ge r5 r5 r6", "ge_r5_r5_r6"},
215 {{ge, r11, r11, r2}, true, ge, "ge r11 r11 r2", "ge_r11_r11_r2"},
242 {{ge, r4, r4, r9}, true, ge, "ge r4 r4 r9", "ge_r4_r4_r9"},
271 {{ge, r14, r14, r12}, true, ge, "ge r14 r14 r12", "ge_r14_r14_r12"},
333 {{ge, r6, r6, r11}, true, ge, "ge r6 r6 r11", "ge_r6_r6_r11"},
342 {{ge, r13, r13, r4}, true, ge, "ge r13 r13 r4", "ge_r13_r13_r4"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"},
137 {{ge, r7, r3, ASR, 28}, true, ge, "ge r7 r3 ASR 28", "ge_r7_r3_ASR_28"},
139 {{ge, r3, r7, LSR, 23}, true, ge, "ge r3 r7 LSR 23", "ge_r3_r7_LSR_23"},
140 {{ge, r3, r3, LSR, 25}, true, ge, "ge r3 r3 LSR 25", "ge_r3_r3_LSR_25"},
157 {{ge, r0, r5, ASR, 24}, true, ge, "ge r0 r5 ASR 24", "ge_r0_r5_ASR_24"},
195 {{ge, r0, r4, LSR, 24}, true, ge, "ge r0 r4 LSR 24", "ge_r0_r4_LSR_24"},
214 {{ge, r3, r7, LSR, 17}, true, ge, "ge r3 r7 LSR 17", "ge_r3_r7_LSR_17"},
218 {{ge, r7, r7, ASR, 20}, true, ge, "ge r7 r7 ASR 20", "ge_r7_r7_ASR_20"},
236 {{ge, r7, r4, LSR, 15}, true, ge, "ge r7 r4 LSR 15", "ge_r7_r4_LSR_15"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc245 {{ge, r13, r13, r0}, true, ge, "ge r13 r13 r0", "ge_r13_r13_r0"},
246 {{ge, r13, r13, r1}, true, ge, "ge r13 r13 r1", "ge_r13_r13_r1"},
247 {{ge, r13, r13, r2}, true, ge, "ge r13 r13 r2", "ge_r13_r13_r2"},
248 {{ge, r13, r13, r3}, true, ge, "ge r13 r13 r3", "ge_r13_r13_r3"},
249 {{ge, r13, r13, r4}, true, ge, "ge r13 r13 r4", "ge_r13_r13_r4"},
250 {{ge, r13, r13, r5}, true, ge, "ge r13 r13 r5", "ge_r13_r13_r5"},
251 {{ge, r13, r13, r6}, true, ge, "ge r13 r13 r6", "ge_r13_r13_r6"},
252 {{ge, r13, r13, r7}, true, ge, "ge r13 r13 r7", "ge_r13_r13_r7"},
253 {{ge, r13, r13, r8}, true, ge, "ge r13 r13 r8", "ge_r13_r13_r8"},
254 {{ge, r13, r13, r9}, true, ge, "ge r13 r13 r9", "ge_r13_r13_r9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc173 {{ge, r0, r0}, true, ge, "ge r0 r0", "ge_r0_r0"},
174 {{ge, r1, r1}, true, ge, "ge r1 r1", "ge_r1_r1"},
175 {{ge, r2, r2}, true, ge, "ge r2 r2", "ge_r2_r2"},
176 {{ge, r3, r3}, true, ge, "ge r3 r3", "ge_r3_r3"},
177 {{ge, r4, r4}, true, ge, "ge r4 r4", "ge_r4_r4"},
178 {{ge, r5, r5}, true, ge, "ge r5 r5", "ge_r5_r5"},
179 {{ge, r6, r6}, true, ge, "ge r6 r6", "ge_r6_r6"},
180 {{ge, r7, r7}, true, ge, "ge r7 r7", "ge_r7_r7"},
Dtest-macro-assembler-cond-rd-rn-pc-a32.cc397 {{ge, r0, r15}, "ge, r0, r15", "ge_r0_r15"},
398 {{ge, r1, r15}, "ge, r1, r15", "ge_r1_r15"},
399 {{ge, r2, r15}, "ge, r2, r15", "ge_r2_r15"},
400 {{ge, r3, r15}, "ge, r3, r15", "ge_r3_r15"},
401 {{ge, r4, r15}, "ge, r4, r15", "ge_r4_r15"},
402 {{ge, r5, r15}, "ge, r5, r15", "ge_r5_r15"},
403 {{ge, r6, r15}, "ge, r6, r15", "ge_r6_r15"},
404 {{ge, r7, r15}, "ge, r7, r15", "ge_r7_r15"},
405 {{ge, r8, r15}, "ge, r8, r15", "ge_r8_r15"},
406 {{ge, r9, r15}, "ge, r9, r15", "ge_r9_r15"},
[all …]
/external/bcc/tools/
Dcpuunclaimed.py245 for ge in sorted(group):
247 g_time = ge
248 g_max = ge
254 for ge in sorted(group):
255 lens[samples[ge]['cpu']] = samples[ge]['len']
257 offs[samples[ge]['cpu']] = ge - g_time
272 for ge in group:
273 if samples[ge]['len'] > 0:
275 if samples[ge]['len'] > 1:
276 g_queued += samples[ge]['len'] - 1
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dsel.asm9 sel.ge(8) g3<1>D g2<0,1,0>D -1D { align1 1Q };
11 sel.ge(16) g3<1>D g2<0,1,0>D -1D { align1 1H };
15 sel.ge(8) g64<1>F g9<8,8,1>F 0x0F /* 0F */ { align1 1Q };
17 sel.ge(16) g24<1>F g20<8,8,1>F 0x0F /* 0F */ { align1 1H };
22 sel.ge(8) g3<1>.yF g7<4>.xF 0x0F /* 0F */ { align16 1Q };
28 sel.ge(8) g4<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 1Q };
30 sel.ge(16) g4<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 1H };
32 sel.ge(8) g21<1>.xyD g1<0>.xyyyD g1<0>.zwwwD { align16 1Q };
34 sel.ge(8) g22<1>UD g1<0>UD g1.4<0>.xUD { align16 1Q };
41 sel.ge(8) g13<1>.xF g1<0>.wF g1<0>.zF { align16 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dcmp.asm1 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
8 cmp.ge.f0.0(8) g33<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
10 cmp.ge.f0.0(8) g2<1>F g23<8,8,1>F g51<0,1,0>F { align1 1Q };
12 cmp.ge.f0.0(8) g3<1>F g4<8,8,1>F g51<0,1,0>F { align1 2Q };
18 cmp.ge.f0.0(8) g9<1>.xF g1<0>.xF g1<0>.yF { align16 1Q };
39 cmp.ge.f0.0(8) g12<1>.xD g5.4<0>.zD g5.4<0>.wD { align16 1Q };
60 cmp.ge.f0.0(8) g9<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 2Q };
69 cmp.ge.f0.0(8) null<1>D g20<8,8,1>D g4<0,1,0>D { align1 1Q switch };
70 cmp.ge.f0.0(16) null<1>D g13<8,8,1>D g6<0,1,0>D { align1 1H switch };
73 cmp.ge.f0.0(8) g74<1>.xD g1<0>.xD 16D { align16 1Q };
[all …]
/external/bzip2/
Dcompress.c241 Int32 v, t, i, j, gs, ge, totc, bt, bc, iter; in sendMTFValues() local
288 ge = gs-1; in sendMTFValues()
290 while (aFreq < tFreq && ge < alphaSize-1) { in sendMTFValues()
291 ge++; in sendMTFValues()
292 aFreq += s->mtfFreq[ge]; in sendMTFValues()
295 if (ge > gs in sendMTFValues()
298 aFreq -= s->mtfFreq[ge]; in sendMTFValues()
299 ge--; in sendMTFValues()
305 nPart, gs, ge, aFreq, in sendMTFValues()
309 if (v >= gs && v <= ge) in sendMTFValues()
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dcmp.asm1 cmp.ge.f0.0(8) null<1>D g12<8,8,1>D 16D { align1 };
2 cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr };
3 cmp.ge.f0.0(8) null<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 };
4 cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
5 cmp.ge.f0.0(8) null<1>F g5<4>.xF 0x0F /* 0F */ { align16 };
9 cmp.ge.f0.0(8) g6<1>F g4<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 };
10 cmp.ge.f0.0(16) g12<1>F g8<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 compr };
11 cmp.ge.f0.0(8) null<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
12 cmp.ge.f0.0(16) null<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
16 cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dsel.asm9 sel.ge(8) g64<1>F g5<8,8,1>F 0x0F /* 0F */ { align1 1Q };
10 sel.ge(16) g17<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 1H };
11 sel.ge(8) g3<1>.yF g7<4>.xF 0x0F /* 0F */ { align16 1Q };
18 sel.ge(8) g20<1>F g19<8,8,1>F g16<8,8,1>F { align1 1Q };
19 sel.ge(16) g12<1>F g10<8,8,1>F g8<8,8,1>F { align1 1H };
23 sel.ge(8) g13<1>.xF g1<0>.wF g1<0>.zF { align16 1Q };
30 sel.ge(8) g18<1>.zD g18<4>.zD 1D { align16 1Q };
33 sel.ge(8) g4<1>D g3<0,1,0>D -252D { align1 1Q };
35 sel.ge(16) g4<1>D g3<0,1,0>D -252D { align1 1H };
50 sel.ge(8) g22<1>.xD g3.4<0>.xD g5.4<0>.xD { align16 1Q };
[all …]
Dcmp.asm1 cmp.ge.f0.0(8) g38<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
5 cmp.ge.f0.0(8) null<1>F g38<4>.xF g36<4>.xF { align16 1Q };
7 cmp.ge.f0.0(8) null<1>UD g18<4>.xUD g17<4>.xUD { align16 1Q };
19 cmp.ge.f0.0(8) g23<1>F g21<8,8,1>F g20<8,8,1>F { align1 1Q };
21 cmp.ge.f0.0(16) g27<1>F g23<8,8,1>F g2<8,8,1>F { align1 1H };
37 cmp.ge.f0.0(8) null<1>.xD g5<4>.xD 4D { align16 1Q };
62 cmp.ge.f0.0(8) g5<1>D g2<0,1,0>D 1D { align1 1Q };
63 cmp.ge.f0.0(16) g7<1>D g2<0,1,0>D 1D { align1 1H };
72 cmp.ge.f0.0(8) g77<1>.xD g2<0>.xD 16D { align16 1Q };
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