| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 78 .getImm(); in getCFAluSize()
85 .getImm(); in isCFAluEnabled()
126 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
127 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
129 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
130 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
142 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
143 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 88 .getImm(); in getCFAluSize()
95 .getImm(); in isCFAluEnabled()
136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
137 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
139 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
152 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 88 .getImm(); in getCFAluSize()
95 .getImm(); in isCFAluEnabled()
136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
137 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
139 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
152 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
153 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
114 .addImm(MI->getOperand(0).getImm()) in EmitInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
194 MI->getOperand(4).getImm() == 4) { in printInst()
289 switch (MI->getOperand(0).getImm()) { in printInst()
318 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
[all …]
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
194 MI->getOperand(4).getImm() == 4) { in printInst()
289 switch (MI->getOperand(0).getImm()) { in printInst()
318 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
[all …]
|
| /external/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
| D | VEInstPrinter.cpp | 68 int32_t TruncatedImm = static_cast<int32_t>(MO.getImm()); in printOperand()
90 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
99 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
107 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
112 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
134 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
139 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
141 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
[all …]
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
96 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
145 MI->getOperand(3).getImm() == -4) { in printInst()
174 MI->getOperand(4).getImm() == 4) { in printInst()
279 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
323 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
352 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
[all …]
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
137 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
137 .addImm(MI->getOperand(0).getImm()) in EmitInstruction()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 36 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
41 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
46 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand()
51 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
56 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
61 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
66 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
71 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
93 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
101 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
[all …]
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
93 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
94 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
116 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
148 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
244 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
251 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand()
258 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU3ImmOperand()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
138 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
[all …]
|
| D | LanaiInstPrinter.cpp | 49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
167 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
193 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
138 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
[all …]
|
| D | LanaiInstPrinter.cpp | 49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
167 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
193 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
[all …]
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 118 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
141 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
199 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
204 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
207 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
208 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
209 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
211 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 40 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
45 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
62 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
67 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
72 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
78 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
83 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
105 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
114 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 63 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
68 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
76 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
85 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
90 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
95 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
101 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
106 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
128 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
137 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCInstPrinter.cpp | 97 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
98 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
99 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
131 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
132 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
154 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
178 unsigned char L = MI->getOperand(0).getImm(); in printInst()
204 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
300 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
309 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
[all …]
|
| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
49 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
50 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
59 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
64 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
153 OS << formatHex(Op.getImm()); in printOperand()
164 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
178 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
190 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCInstPrinter.cpp | 115 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
116 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
117 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
139 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
140 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
162 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
186 unsigned char L = MI->getOperand(0).getImm(); in printInst()
218 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
314 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
323 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 208 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
240 return MO.getImm(); in getAdrLabelOpValue()
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
340 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
341 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 208 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
240 return MO.getImm(); in getAdrLabelOpValue()
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
340 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
341 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 246 int64_t getImm() const { in getImm() function
317 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
318 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
319 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
320 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
321 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
322 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm()
323 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
325 isUInt<6>(getImm()) && in isU6ImmX2()
326 (getImm() & 1) == 0; } in isU6ImmX2()
[all …]
|