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Searched refs:getReg (Results 1 – 25 of 1453) sorted by relevance

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/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DConstantFoldingTest.cpp31 bool match = mi_match(MIBCAdd.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
38 match = mi_match(MIBCAdd1.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
50 match = mi_match(MIBCSub.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
58 match = mi_match(MIBCSext1.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
66 match = mi_match(MIBCSext2.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
84 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0), in TEST_F()
85 MIBCst2.getReg(0), *MRI); in TEST_F()
89 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0), in TEST_F()
90 MIBFCst2.getReg(0), *MRI); in TEST_F()
96 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1.getReg(0), in TEST_F()
[all …]
DPatternMatchTest.cpp39 bool match = mi_match(MIBCst.getReg(0), *MRI, m_ICst(Cst)); in TEST_F()
53 mi_match(MIBAdd.getReg(0), *MRI, m_GAdd(m_Reg(), m_Reg())); in TEST_F()
56 match = mi_match(MIBAdd.getReg(0), *MRI, in TEST_F()
66 match = mi_match(MIBMul.getReg(0), *MRI, in TEST_F()
69 EXPECT_EQ(Src0, MIBAdd.getReg(0)); in TEST_F()
73 match = mi_match(MIBMul.getReg(0), *MRI, in TEST_F()
85 match = mi_match(MIBMul2.getReg(0), *MRI, in TEST_F()
93 match = mi_match(MIBSub.getReg(0), *MRI, in TEST_F()
100 match = mi_match(MIBFMul.getReg(0), *MRI, in TEST_F()
109 match = mi_match(MIBFSub.getReg(0), *MRI, in TEST_F()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
276 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
281 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
286 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
287 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
292 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
297 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
[all …]
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
345 MaskRegName = getRegName(MI->getOperand(2).getReg()); in getMaskName()
384 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
393 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
394 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
400 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
409 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
410 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
416 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
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/external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/
Dllvm-prefer-register-over-unsigned.cpp20 llvm::Register getReg();
24 unsigned Reg1 = getReg(); in apply_1()
32 unsigned Reg2 = getReg(); in apply_2()
44 unsigned Reg3 = getReg(); in apply_3()
52 llvm::Register Reg1 = getReg(); in done_1()
59 Register Reg2 = getReg(); in done_2()
67 Register Reg3 = getReg(); in done_3()
97 fn1(getReg()); in do_nothing_4()
104 fn2(getReg()); in do_nothing_5()
111 Register Reg6{getReg()}; in do_nothing_6()
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/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DGISelKnownBits.cpp38 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
53 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
190 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
230 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
232 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
239 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
241 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
249 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
255 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
257 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
[all …]
DCombinerHelper.cpp89 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
90 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
94 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
95 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
121 Register Reg = MO.getReg(); in matchCombineConcatVectors()
130 Ops.push_back(BuildVecMO.getReg()); in matchCombineConcatVectors()
139 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
146 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
159 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
190 LLT DstType = MRI.getType(MI.getOperand(0).getReg()); in matchCombineShuffleVector()
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DLegalizerHelper.cpp255 Regs[StartIdx + I] = MI.getOperand(I).getReg(); in getUnmergeResults()
295 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces()
297 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
304 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); in buildLCMMergePieces()
342 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
344 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces()
360 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); in buildLCMMergePieces()
560 Args.push_back({MI.getOperand(i).getReg(), OpType}); in simpleLibcall()
561 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, in simpleLibcall()
573 Register Reg = MI.getOperand(i).getReg(); in createMemLibcall()
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/external/llvm-project/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp123 RegsToInvalidate.insert(MI->getOperand(0).getReg().asMCReg()); in invalidateRegister()
124 RegsToInvalidate.insert(MI->getOperand(1).getReg().asMCReg()); in invalidateRegister()
146 markRegsUnavailable({MI->getOperand(0).getReg().asMCReg()}, TRI); in clobberRegister()
157 MCRegister Def = MI->getOperand(0).getReg().asMCReg(); in trackCopy()
158 MCRegister Src = MI->getOperand(1).getReg().asMCReg(); in trackCopy()
205 !TRI.isSubRegisterEq(AvailCopy->getOperand(1).getReg(), Reg)) in findAvailBackwardCopy()
208 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailBackwardCopy()
209 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailBackwardCopy()
229 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg)) in findAvailCopy()
234 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailCopy()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp121 RegsToInvalidate.insert(MI->getOperand(0).getReg()); in invalidateRegister()
122 RegsToInvalidate.insert(MI->getOperand(1).getReg()); in invalidateRegister()
144 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI); in clobberRegister()
155 Register Def = MI->getOperand(0).getReg(); in trackCopy()
156 Register Src = MI->getOperand(1).getReg(); in trackCopy()
202 !TRI.isSubRegisterEq(AvailCopy->getOperand(1).getReg(), Reg)) in findAvailBackwardCopy()
205 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailBackwardCopy()
206 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailBackwardCopy()
226 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg)) in findAvailCopy()
231 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailCopy()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp126 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
127 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
141 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
142 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
153 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
164 Register Reg = Op.getReg(); in applyBank()
308 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
313 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
469 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
495 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
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/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp101 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
102 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
107 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass : in processBlock()
109 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
110 IsVRReg(SrcMO.getReg(), MRI) || in processBlock()
111 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
112 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
121 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 : in processBlock()
126 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
127 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
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/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp67 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
68 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
82 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
83 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
94 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
104 Register Reg = Op.getReg(); in applyBank()
250 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
255 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
427 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
453 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp386 Args.push_back({MI.getOperand(i).getReg(), OpType}); in simpleLibcall()
387 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, in simpleLibcall()
400 Register Reg = MI.getOperand(i).getReg(); in createMemLibcall()
485 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, in conversionLibcall()
486 {{MI.getOperand(1).getReg(), FromType}}); in conversionLibcall()
491 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); in libcall()
539 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
540 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
551 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in libcall()
552 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); in libcall()
[all …]
DGISelKnownBits.cpp66 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
134 if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() && in computeKnownBitsImpl()
136 MRI.getType(Src.getReg()).isValid()) { in computeKnownBitsImpl()
138 computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth); in computeKnownBitsImpl()
158 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
163 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
170 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
172 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
184 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
197 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp90 printRegName(O, Dst.getReg()); in printInst()
92 printRegName(O, MO1.getReg()); in printInst()
95 printRegName(O, MO2.getReg()); in printInst()
112 printRegName(O, Dst.getReg()); in printInst()
114 printRegName(O, MO1.getReg()); in printInst()
130 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
144 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
149 printRegName(O, MI->getOperand(1).getReg()); in printInst()
159 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
173 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp110 printRegName(O, Dst.getReg()); in printInst()
112 printRegName(O, MO1.getReg()); in printInst()
115 printRegName(O, MO2.getReg()); in printInst()
132 printRegName(O, Dst.getReg()); in printInst()
134 printRegName(O, MO1.getReg()); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
169 printRegName(O, MI->getOperand(1).getReg()); in printInst()
179 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
193 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp110 printRegName(O, Dst.getReg()); in printInst()
112 printRegName(O, MO1.getReg()); in printInst()
115 printRegName(O, MO2.getReg()); in printInst()
132 printRegName(O, Dst.getReg()); in printInst()
134 printRegName(O, MO1.getReg()); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
169 printRegName(O, MI->getOperand(1).getReg()); in printInst()
179 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
193 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp202 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
203 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
220 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
261 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
262 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
190 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
208 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
229 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
239 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
249 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]

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