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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
137 MRI.getRegClass(SrcReg) : in getCopyRegClasses()
145 MRI.getRegClass(DstReg) : in getCopyRegClasses()
183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
276 if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) in runOnMachineFunction()
319 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { in runOnMachineFunction()
357 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
358 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
359 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
DSILowerI1Copies.cpp86 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in runOnMachineFunction()
102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction()
103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction()
DSIInstrInfo.cpp336 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg()); in shouldClusterMemOps()
1246 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
1249 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
1293 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))) in FoldImmediate()
1296 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
1548 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); in isImmOperandLegal()
1588 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
1685 RI.getRegClass(RegClass)->getSize())) { in verifyInstruction()
1713 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
1856 return MRI.getRegClass(Reg); in getOpRegClass()
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/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp239 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { in printRegOperand()
242 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { in printRegOperand()
245 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { in printRegOperand()
248 } else if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(reg)) { in printRegOperand()
251 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { in printRegOperand()
254 } else if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(reg)) { in printRegOperand()
257 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { in printRegOperand()
260 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { in printRegOperand()
263 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { in printRegOperand()
266 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) { in printRegOperand()
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/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
48 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
50 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
60 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) && in AArch64RegisterBankInfo()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
/external/llvm-project/llvm/test/TableGen/
DAsmPredicateCombiningRISCV.td69 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
76 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
82 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
90 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
97 // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
165 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/external/llvm-project/llvm/lib/Target/ARM/
DARMRegisterBankInfo.cpp147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
162 *TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
641 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
175 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp442 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || in getAVOperandEncoding()
443 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || in getAVOperandEncoding()
444 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || in getAVOperandEncoding()
445 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || in getAVOperandEncoding()
446 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || in getAVOperandEncoding()
447 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || in getAVOperandEncoding()
448 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || in getAVOperandEncoding()
449 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) in getAVOperandEncoding()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp64 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in MaybeRewriteToDrop()
91 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); in MaybeRewriteToFallthrough()
159 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
175 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
182 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
247 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
677 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
678 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
679 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
787 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp160 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
174 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
181 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
221 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
245 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
290 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
707 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
708 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
709 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
827 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
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/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
279 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
531 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
532 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
548 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
554 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
658 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
132 MRI.getRegClass(AddendSrcReg)) in processBlock()
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
237 MRI.getRegClass(OldFMAReg))) in processBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
128 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() function in X86InstructionSelector
197 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
200 return getRegClass(Ty, RegBank); in getRegClass()
248 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
278 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
727 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
728 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
809 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectZext()
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