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Searched refs:getSlotIndexes (Results 1 – 25 of 44) sorted by relevance

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/external/llvm-project/llvm/lib/CodeGen/
DSplitKit.cpp226 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); in calcLiveBlockInfo()
378 LICalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
381 LICalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
526 SlotIndexes &Indexes = *LIS.getSlotIndexes(); in buildSingleSubRegCopy()
549 SlotIndexes &Indexes = *LIS.getSlotIndexes(); in buildCopy()
673 SlotIndexes &Indexes = *LIS.getSlotIndexes(); in defFromParent()
1188 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB); in transferValues()
1305 SubLIC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in extendPHIKillRanges()
1308 LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes()); in extendPHIKillRanges()
1401 SubLIC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in rewriteAssigned()
[all …]
DLiveIntervals.cpp195 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeVirtRegInterval()
277 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeRegUnitRange()
634 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in extendToIndices()
1444 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI); in findLastUseBefore()
1454 SlotIndexes *Indexes = LIS.getSlotIndexes(); in findLastUseBefore()
1732 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in constructMainRangeFromSubranges()
DLiveRegMatrix.cpp173 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes()); in checkRegUnitInterference()
DCalcSpillWeights.cpp286 if (ShouldUpdateLI && LI.isZeroLength(LIS.getSlotIndexes()) && in weightCalcHelper()
DRegisterCoalescer.cpp965 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in removeCopyByCommutingDef()
1220 *LIS->getSlotIndexes()); in removePartialRedundancy()
1773 ? LIS->getSlotIndexes()->getIndexBefore(*UseMI) in updateRegDefsUses()
2122 SlotIndexes *Indexes = LIS->getSlotIndexes(); in joinReservedPhysReg()
2405 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()), in JoinVals()
3352 *LIS->getSlotIndexes(), *TRI, ComposeSubRegIdx); in mergeSubRangeInto()
3488 const SlotIndexes &Slots = *LIS->getSlotIndexes(); in buildVRegToDbgValueMap()
DRenameIndependentSubregs.cpp304 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in computeMainRangesFixFlags()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DSplitKit.cpp231 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); in calcLiveBlockInfo()
383 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
386 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
523 SlotIndexes &Indexes = *LIS.getSlotIndexes(); in buildSingleSubRegCopy()
546 SlotIndexes &Indexes = *LIS.getSlotIndexes(); in buildCopy()
1176 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB); in transferValues()
1293 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in extendPHIKillRanges()
1296 LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes()); in extendPHIKillRanges()
1389 SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in rewriteAssigned()
1392 LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes()); in rewriteAssigned()
[all …]
DLiveIntervals.cpp197 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeVirtRegInterval()
270 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeRegUnitRange()
627 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in extendToIndices()
1424 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI); in findLastUseBefore()
1434 SlotIndexes *Indexes = LIS.getSlotIndexes(); in findLastUseBefore()
1682 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in constructMainRangeFromSubranges()
DLiveRegMatrix.cpp173 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes()); in checkRegUnitInterference()
DCalcSpillWeights.cpp288 if (updateLI && li.isZeroLength(LIS.getSlotIndexes()) && in weightCalcHelper()
DRenameIndependentSubregs.cpp304 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in computeMainRangesFixFlags()
/external/llvm/lib/CodeGen/
DSplitKit.cpp206 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); in calcLiveBlockInfo()
360 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
363 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, in reset()
468 Def = LIS.getSlotIndexes() in defFromParent()
974 std::tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(&*MBB); in transferValues()
1274 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum); in splitLiveThroughBlock()
1377 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); in splitRegInBlock()
1469 std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); in splitRegOutBlock()
DLiveIntervalAnalysis.cpp192 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeVirtRegInterval()
260 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in computeRegUnitRange()
579 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in extendToIndices()
1325 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI); in findLastUseBefore()
1335 SlotIndexes *Indexes = LIS.getSlotIndexes(); in findLastUseBefore()
1573 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator()); in constructMainRangeFromSubranges()
DLiveRegMatrix.cpp166 return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes()); in checkRegUnitInterference()
DCalcSpillWeights.cpp222 if (li.isZeroLength(LIS.getSlotIndexes()) && in calculateSpillWeightAndHint()
DRenameIndependentSubregs.cpp292 const SlotIndexes &Indexes = *LIS->getSlotIndexes(); in computeMainRangesFixFlags()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.h206 auto &SII = *LIS.getSlotIndexes(); in getLiveRegMap()
DSIFormMemoryClauses.cpp318 SlotIndexes *Ind = LIS->getSlotIndexes(); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNRegPressure.h214 auto &SII = *LIS.getSlotIndexes(); in getLiveRegMap()
DSIFormMemoryClauses.cpp318 SlotIndexes *Ind = LIS->getSlotIndexes(); in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DLiveIntervalAnalysis.h187 SlotIndexes *getSlotIndexes() const { in getSlotIndexes() function
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveIntervals.h211 SlotIndexes *getSlotIndexes() const { in getSlotIndexes() function
/external/llvm-project/llvm/include/llvm/CodeGen/
DLiveIntervals.h211 SlotIndexes *getSlotIndexes() const { in getSlotIndexes() function
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp266 const SlotIndexes &Indexes = *LIS.getSlotIndexes(); in shouldCoalesce()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp259 const SlotIndexes &Indexes = *LIS.getSlotIndexes(); in shouldCoalesce()

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