| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
291 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
292 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
301 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
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| D | AMDGPURegisterInfo.h | 35 unsigned getSubRegFromChannel(unsigned Channel) const;
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| D | AMDGPURegisterInfo.cpp | 39 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { in getSubRegFromChannel() function in AMDGPURegisterInfo
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| D | R600ControlFlowFinalizer.cpp | 296 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
305 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
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| D | AMDGPUISelDAGToDAG.cpp | 341 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, in Select()
354 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); in Select()
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| D | SIInstrInfo.cpp | 2178 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
2187 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 222 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
227 unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
228 unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
237 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
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| D | AMDGPURegisterInfo.h | 31 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
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| D | AMDGPURegisterInfo.cpp | 75 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel, unsigned NumRegs) { in getSubRegFromChannel() function in AMDGPURegisterInfo
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| D | SIShrinkInstructions.cpp | 427 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex()
430 Sub = TRI.getSubRegFromChannel(I + countTrailingZeros(LM.getAsInteger())); in getSubRegForIndex()
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| D | R600ControlFlowFinalizer.cpp | 311 AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
320 AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
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| D | R600InstrInfo.cpp | 80 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
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| D | AMDGPUISelDAGToDAG.cpp | 710 unsigned Sub = AMDGPURegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
720 unsigned Sub = AMDGPURegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 222 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
227 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction()
228 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction()
237 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
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| D | R600RegisterInfo.h | 27 static unsigned getSubRegFromChannel(unsigned Channel);
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| D | R600RegisterInfo.cpp | 26 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { in getSubRegFromChannel() function in R600RegisterInfo
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| D | SIAddIMGInit.cpp | 156 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx)); in runOnMachineFunction()
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| D | SIRegisterInfo.h | 55 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
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| D | R600ControlFlowFinalizer.cpp | 310 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
319 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
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| D | SIShrinkInstructions.cpp | 432 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex()
434 Sub = TRI.getSubRegFromChannel(I + TRI.getChannelFromSubReg(Sub)); in getSubRegForIndex()
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| D | AMDGPUISelDAGToDAG.cpp | 694 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
695 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
705 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector()
706 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
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| D | SIRegisterInfo.cpp | 194 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel, in getSubRegFromChannel() function in SIRegisterInfo
848 : Register(getSubReg(ValueReg, getSubRegFromChannel(i))); in buildSpillLoadStore()
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| D | SIInstrInfo.cpp | 661 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
4737 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
4746 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
4867 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx)); in emitLoadSRsrcFromVGPRLoop()
4871 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx + 1)); in emitLoadSRsrcFromVGPRLoop()
4891 Cmp.addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx, 2)); in emitLoadSRsrcFromVGPRLoop()
4913 .addImm(TRI->getSubRegFromChannel(Channel++)); in emitLoadSRsrcFromVGPRLoop()
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| D | R600InstrInfo.cpp | 80 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | inst-select-insert.xfail.mir | 25 # getSubRegFromChannel current does not handle cases > 128-bits
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