| /external/arm-trusted-firmware/plat/mediatek/mt8192/ |
| D | plat_mt_gic.c | 37 .gicr_base = MT_GIC_RDIST_BASE,
80 uintptr_t gicr_base; in mt_gic_rdistif_init() local
83 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
86 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
87 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
91 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
98 uintptr_t gicr_base; in mt_gic_rdistif_save() local
101 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
103 gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); in mt_gic_rdistif_save()
104 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
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| /external/arm-trusted-firmware/drivers/arm/gic/v3/ |
| D | arm_gicv3_common.c | 30 uintptr_t gicr_base = 0; in arm_gicv3_distif_pre_save() local
41 gicr_base = gicv3_driver_data->rdistif_base_addrs[i]; in arm_gicv3_distif_pre_save()
42 assert(gicr_base); in arm_gicv3_distif_pre_save()
43 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); in arm_gicv3_distif_pre_save()
44 assert(gicr_read_waker(gicr_base) & WAKER_PS_BIT); in arm_gicv3_distif_pre_save()
47 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_pre_save()
61 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT); in arm_gicv3_distif_pre_save()
64 while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT)) in arm_gicv3_distif_pre_save()
74 uintptr_t gicr_base; in arm_gicv3_distif_post_restore() local
84 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_post_restore()
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| D | gicv3_helpers.c | 22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) in gicv3_rdistif_mark_core_awake() argument
28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); in gicv3_rdistif_mark_core_awake()
31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); in gicv3_rdistif_mark_core_awake()
34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { in gicv3_rdistif_mark_core_awake()
42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) in gicv3_rdistif_mark_core_asleep() argument
45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); in gicv3_rdistif_mark_core_asleep()
48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { in gicv3_rdistif_mark_core_asleep()
59 uintptr_t gicr_base, in gicv3_rdistif_base_addrs_probe() argument
65 uintptr_t rdistif_base = gicr_base; in gicv3_rdistif_base_addrs_probe()
221 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) in gicv3_ppi_sgi_config_defaults() argument
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| D | gicv3_main.c | 141 if (plat_driver_data->gicr_base != 0U) { in gicv3_driver_init()
150 plat_driver_data->gicr_base, in gicv3_driver_init()
228 uintptr_t gicr_base; in gicv3_rdistif_init() local
245 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_rdistif_init()
246 assert(gicr_base != 0U); in gicv3_rdistif_init()
249 gicv3_ppi_sgi_config_defaults(gicr_base); in gicv3_rdistif_init()
251 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, in gicv3_rdistif_init()
278 uintptr_t gicr_base; in gicv3_cpuif_enable() local
288 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_cpuif_enable()
289 gicv3_rdistif_mark_core_awake(gicr_base); in gicv3_cpuif_enable()
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| D | gic-x00.c | 109 uintptr_t gicr_base; in get_gicr_base() local
115 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in get_gicr_base()
116 assert(gicr_base != 0UL); in get_gicr_base()
118 return gicr_base; in get_gicr_base()
121 static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base) in gicv3_redists_need_power_mgmt() argument
123 uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); in gicv3_redists_need_power_mgmt()
152 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_off() local
155 if (gicv3_redists_need_power_mgmt(gicr_base)) { in gicv3_rdistif_off()
156 gic600_pwr_off(gicr_base); in gicv3_rdistif_off()
167 uintptr_t gicr_base = get_gicr_base(proc_num); in gicv3_rdistif_on() local
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| D | gicv3_private.h | 236 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
237 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
245 uintptr_t gicr_base,
247 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
248 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
340 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) in gicr_wait_for_pending_write() argument
342 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) { in gicr_wait_for_pending_write()
346 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) in gicr_wait_for_upstream_pending_write() argument
348 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) { in gicr_wait_for_upstream_pending_write()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_mt_gic.c | 34 .gicr_base = MT_GIC_RDIST_BASE,
85 uintptr_t gicr_base; in mt_gic_rdistif_init() local
88 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
91 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
92 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
96 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
113 uintptr_t gicr_base; in mt_gic_rdistif_save() local
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
118 gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); in mt_gic_rdistif_save()
119 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
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| /external/arm-trusted-firmware/plat/ti/k3/common/ |
| D | k3_gicv3.c | 45 uintptr_t gicr_base = 0; in k3_gic_driver_init() local
52 gicr_base = gicr_check; in k3_gic_driver_init()
57 assert(gicr_base != 0); in k3_gic_driver_init()
66 k3_gic_data.gicr_base = gicr_base; in k3_gic_driver_init()
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_gicv3.c | 62 .gicr_base = 0x5fe40000,
71 .gicr_base = 0x5fe80000,
80 .gicr_base = 0x5fe80000,
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| /external/arm-trusted-firmware/plat/arm/board/arm_fpga/ |
| D | fpga_gicv3.c | 57 &fpga_gicv3_driver_data.gicr_base, NULL); in plat_fpga_gic_init()
83 return gicv3_rdistif_get_number_frames(fpga_gicv3_driver_data.gicr_base); in fpga_get_nr_gic_cores()
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_gicv3.c | 26 .gicr_base = GICR_BASE,
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_gicv3.c | 41 tegra_gic_data.gicr_base = TEGRA_GICR_BASE; in tegra_gic_setup()
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| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | rockchip_gicv3.c | 40 .gicr_base = PLAT_RK_GICR_BASE,
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| /external/arm-trusted-firmware/plat/brcm/common/ |
| D | brcm_gicv3.c | 44 .gicr_base = PLAT_BRCM_GICR_BASE,
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| /external/arm-trusted-firmware/plat/arm/board/fvp/include/ |
| D | fconf_hw_config_getter.h | 20 uint64_t gicr_base; member
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| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_gicv3.c | 61 .gicr_base = PLAT_SQ_GICR_BASE,
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| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | versal_gicv3.c | 64 .gicr_base = PLAT_VERSAL_GICR_BASE,
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| /external/arm-trusted-firmware/plat/marvell/armada/common/ |
| D | marvell_gicv3.c | 66 .gicr_base = PLAT_MARVELL_GICR_BASE,
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| /external/arm-trusted-firmware/plat/imx/common/ |
| D | plat_imx8_gic.c | 38 .gicr_base = PLAT_GICR_BASE,
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| /external/arm-trusted-firmware/plat/arm/board/fvp/ |
| D | fvp_gicv3.c | 112 gicr_base); in plat_arm_gic_driver_init()
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| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_gicv3.c | 79 .gicr_base = 0U,
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| /external/arm-trusted-firmware/plat/qti/common/src/ |
| D | qti_gic_v3.c | 79 .gicr_base = QTI_GICR_BASE,
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| /external/arm-trusted-firmware/plat/arm/board/fvp/fconf/ |
| D | fconf_hw_config_getter.c | 55 gicv3_config.gicr_base = addr; in fconf_populate_gicv3_config()
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| /external/arm-trusted-firmware/include/drivers/arm/ |
| D | gicv3.h | 431 uintptr_t gicr_base; member
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| /external/arm-trusted-firmware/docs/components/fconf/ |
| D | index.rst | 31 - GICv3 properties: hw_config.gicv3_config.gicr_base
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