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Searched refs:gpu_address (Results 1 – 25 of 38) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c34 uint64_t gpu_address = shadow_regs->gpu_address; in si_build_load_reg() local
43 gpu_address += SI_SHADOWED_UCONFIG_REG_OFFSET; in si_build_load_reg()
48 gpu_address += SI_SHADOWED_CONTEXT_REG_OFFSET; in si_build_load_reg()
53 gpu_address += SI_SHADOWED_SH_REG_OFFSET; in si_build_load_reg()
60 si_pm4_cmd_add(pm4, gpu_address); in si_build_load_reg()
61 si_pm4_cmd_add(pm4, gpu_address >> 32); in si_build_load_reg()
Dsi_cp_dma.c206 uint64_t va = (sdst ? sdst->gpu_address : 0) + offset; in si_cp_dma_clear_buffer()
280 va = sctx->scratch_buffer->gpu_address; in si_cp_dma_realign_engine()
312 dst_offset += si_resource(dst)->gpu_address; in si_cp_dma_copy_buffer()
315 src_offset += si_resource(src)->gpu_address; in si_cp_dma_copy_buffer()
586 uint64_t va = buf->gpu_address + offset; in si_cp_write_data()
607 uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset; in si_cp_copy_data()
608 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset; in si_cp_copy_data()
Dsi_dma_cs.c42 uint64_t va = dst->gpu_address + offset; in si_dma_emit_timestamp()
88 offset += sdst->gpu_address; in si_sdma_clear_buffer()
148 dst_offset += sdst->gpu_address; in si_sdma_copy_buffer()
149 src_offset += ssrc->gpu_address; in si_sdma_copy_buffer()
Dsi_buffer.c231 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_alloc_resource()
234 uint64_t start = res->gpu_address; in si_alloc_resource()
251 res->gpu_address, res->gpu_address + res->buf->size, res->buf->size); in si_alloc_resource()
314 sdst->gpu_address = ssrc->gpu_address; in si_replace_buffer_storage()
728 buf->gpu_address = ws->buffer_get_virtual_address(buf->buf); in si_buffer_from_user_memory()
747 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_buffer_from_winsys_buffer()
Dsi_descriptors.c149 desc->gpu_address = si_desc_extract_buffer_address(descriptor); in si_upload_descriptors()
160 desc->gpu_address = 0; in si_upload_descriptors()
172 desc->gpu_address = desc->buffer->gpu_address + buffer_offset; in si_upload_descriptors()
175 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
176 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
282 uint64_t va = buf->gpu_address + offset; in si_set_buf_desc_address()
311 va = tex->buffer.gpu_address; in si_set_mutable_tex_desc_fields()
338 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset; in si_set_mutable_tex_desc_fields()
350 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset; in si_set_mutable_tex_desc_fields()
1045 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); in si_get_buffer_from_descriptors()
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Dsi_state_streamout.c237 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in gfx10_emit_streamout_begin()
261 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in gfx10_emit_streamout_end()
323 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in si_emit_streamout_begin()
369 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in si_emit_streamout_end()
Dsi_compute.c340 va = si_resource(resources[i])->gpu_address; in si_set_global_binding()
350 uint64_t bc_va = sctx->border_color_buffer->gpu_address; in si_emit_initial_compute_regs()
432 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in si_setup_compute_scratch_buffer()
498 shader_va = shader->bo->gpu_address + offset; in si_switch_compute_shader()
540 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in setup_scratch_rsrc_user_sgprs()
624 dispatch_va = dispatch_buf->gpu_address + dispatch_offset; in si_setup_user_sgprs_co_v2()
669 kernel_args_va = input_buffer->gpu_address + kernel_args_offset; in si_upload_compute_input()
776 uint64_t base_va = si_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
Dsi_fence.c96 radeon_emit(cs, scratch->gpu_address); in si_cp_release_mem()
97 radeon_emit(cs, scratch->gpu_address >> 32); in si_cp_release_mem()
115 uint64_t va = scratch->gpu_address; in si_cp_release_mem()
253 uint64_t fence_va = fine->buf->gpu_address + fine->offset; in si_fine_fence_set()
Dsi_compute_prim_discard.c1241 sctx->last_ib_barrier_buf->gpu_address + sctx->last_ib_barrier_buf_offset, in si_dispatch_prim_discard_cs_and_draw()
1256 uint64_t out_indexbuf_va = sctx->index_ring->gpu_address + out_indexbuf_offset; in si_dispatch_prim_discard_cs_and_draw()
1321 uint64_t index_buffers_va = indexbuf_desc->gpu_address + indexbuf_desc_offset; in si_dispatch_prim_discard_cs_and_draw()
1324 uint64_t vs_const_desc_va = sctx->descriptors[vs_const_desc].gpu_address; in si_dispatch_prim_discard_cs_and_draw()
1325 uint64_t vs_sampler_desc_va = sctx->descriptors[vs_sampler_desc].gpu_address; in si_dispatch_prim_discard_cs_and_draw()
1327 ? sctx->vb_descriptors_buffer->gpu_address + sctx->vb_descriptors_offset in si_dispatch_prim_discard_cs_and_draw()
1369 uint64_t shader_va = shader->bo->gpu_address; in si_dispatch_prim_discard_cs_and_draw()
1417 assert((gfx_cs->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_dispatch_prim_discard_cs_and_draw()
1418 sctx->compute_rewind_va = gfx_cs->gpu_address + (gfx_cs->current.cdw + 1) * 4; in si_dispatch_prim_discard_cs_and_draw()
1441 uint32_t count_va = gfx_cs->gpu_address + (gfx_cs->current.cdw + 4) * 4; in si_dispatch_prim_discard_cs_and_draw()
Dsi_texture.c361 tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8; in si_texture_discard_cmask()
489 tex->buffer.gpu_address = new_tex->buffer.gpu_address; in si_reallocate_texture_inplace()
1072 resource->gpu_address = plane0->buffer.gpu_address; in si_texture_create_object()
1081 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); in si_texture_create_object()
1199 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_create_object()
1205 tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->size, in si_texture_create_object()
1622 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_invalidate_storage()
2186 tex->surface.dcc_offset = tex->dcc_separate_buffer->gpu_address; in vi_separate_dcc_try_enable()
Dcik_sdma.c64 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
65 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
210 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[dst_level].offset; in cik_sdma_copy_texture()
211 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[src_level].offset; in cik_sdma_copy_texture()
Dgfx10_query.c223 uint64_t fence_va = query->last->buf->gpu_address; in gfx10_sh_query_end()
450 va = qbuf->buf->gpu_address; in gfx10_sh_query_get_result_resource()
Dsi_query.c839 si_dma_emit_timestamp(sctx, buffer, va - buffer->gpu_address); in si_query_hw_do_emit_start()
892 va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_query_hw_emit_start()
904 si_dma_emit_timestamp(sctx, buffer, va + 32 - buffer->gpu_address); in si_query_hw_do_emit_stop()
978 va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_query_hw_emit_stop()
1062 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset; in si_emit_query_predication()
1072 uint64_t va_base = qbuf->buf->gpu_address; in si_emit_query_predication()
1567 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in si_query_hw_get_result_resource()
Dsi_state_draw.c219 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address; in si_emit_derived_tess_state()
829 index_va = si_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
844 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
887 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset; in si_emit_draw_packets()
1161 va = wait_mem_scratch->gpu_address; in gfx10_emit_cache_flush()
1380 va = wait_mem_scratch->gpu_address; in si_emit_cache_flush()
1520 uint64_t va = buf->gpu_address + offset; in si_upload_vertex_buffer_descriptors()
Dsi_state.c2412 surf->db_depth_base = tex->buffer.gpu_address >> 8; in si_init_depth_surface()
2413 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.stencil_offset) >> 8; in si_init_depth_surface()
2442 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8; in si_init_depth_surface()
2456 (tex->buffer.gpu_address + tex->surface.u.legacy.level[level].offset) >> 8; in si_init_depth_surface()
2458 (tex->buffer.gpu_address + tex->surface.u.legacy.stencil_level[level].offset) >> 8; in si_init_depth_surface()
2513 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8; in si_init_depth_surface()
2926 cb_color_base = tex->buffer.gpu_address >> 8; in si_emit_framebuffer_state()
2937 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8; in si_emit_framebuffer_state()
2951 ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset) >> in si_emit_framebuffer_state()
3744 va = tex->buffer.gpu_address + tex->surface.fmask_offset; in gfx10_make_texture_descriptor()
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/external/mesa3d/src/gallium/drivers/r600/
Devergreen_hw_context.c49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer()
50 src_offset += rsrc->gpu_address; in evergreen_dma_copy_buffer()
99 offset += r600_resource(dst)->gpu_address; in evergreen_cp_dma_clear_buffer()
Dr600_buffer_common.c208 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf); in r600_alloc_resource()
210 res->gpu_address = 0; in r600_alloc_resource()
219 res->gpu_address, res->gpu_address + res->buf->size, in r600_alloc_resource()
274 uint64_t old_gpu_address = rdst->gpu_address; in r600_replace_buffer_storage()
277 rdst->gpu_address = rsrc->gpu_address; in r600_replace_buffer_storage()
657 rbuffer->gpu_address = in r600_buffer_from_user_memory()
660 rbuffer->gpu_address = 0; in r600_buffer_from_user_memory()
Dr600_streamout.c196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address; in r600_emit_streamout_begin()
221 uint64_t va = t[i]->buf_filled_size->gpu_address + in r600_emit_streamout_begin()
267 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in r600_emit_streamout_end()
Devergreen_state.c656 va = tmp->resource.gpu_address + params->offset; in evergreen_fill_buffer_resource_words()
701 if (tmp->resource.gpu_address) in texture_buffer_sampler_view()
826 va = tmp->resource.gpu_address; in evergreen_fill_tex_resource_words()
1105 color->offset = (res->gpu_address + first_element) >> 8; in evergreen_set_color_surface_buffer()
1131 color->offset += rtex->resource.gpu_address; in evergreen_set_color_surface_common()
1276 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8; in evergreen_set_color_surface_common()
1363 offset = rtex->resource.gpu_address; in evergreen_init_depth_surface()
1415 stencil_offset += rtex->resource.gpu_address; in evergreen_init_depth_surface()
1430 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; in evergreen_init_depth_surface()
1775 …set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8); in evergreen_emit_image_state()
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Dr600_hw_context.c466 va = buf->gpu_address + offset; in r600_emit_pfp_sync_me()
516 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer()
517 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
Dr600_texture.c342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
409 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_reallocate_texture_inplace()
737 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in r600_texture_alloc_cmask_separate()
982 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf); in r600_texture_create_object()
1009 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object()
1013 rtex->resource.gpu_address, in r600_texture_create_object()
1014 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object()
1284 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage()
Dr600_uvd.c128 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in r600_video_buffer_create()
Dr600_query.c799 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_start()
886 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_stop()
954 uint64_t va_base = qbuf->buf->gpu_address; in r600_emit_query_predication()
1741 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in r600_query_hw_get_result_resource()
1906 radeon_emit(cs, buffer->gpu_address); in r600_query_fix_enabled_rb_mask()
1907 radeon_emit(cs, buffer->gpu_address >> 32); in r600_query_fix_enabled_rb_mask()
/external/mesa3d/src/amd/vulkan/
Dradv_image.c574 uint64_t gpu_address = radv_buffer_get_va(buffer->bo); in radv_make_buffer_descriptor() local
575 uint64_t va = gpu_address + buffer->offset; in radv_make_buffer_descriptor()
636 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; in si_set_mutable_tex_desc_fields() local
637 uint64_t va = gpu_address + plane->offset; in si_set_mutable_tex_desc_fields()
659 meta_va = gpu_address + plane->surface.dcc_offset; in si_set_mutable_tex_desc_fields()
668 meta_va = gpu_address + plane->surface.htile_offset; in si_set_mutable_tex_desc_fields()
886 uint64_t gpu_address = radv_buffer_get_va(image->bo); in gfx10_make_texture_descriptor() local
892 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; in gfx10_make_texture_descriptor()
1048 uint64_t gpu_address = radv_buffer_get_va(image->bo); in si_make_texture_descriptor() local
1053 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; in si_make_texture_descriptor()
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/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_winsys.h208 uint64_t gpu_address; member

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