Searched refs:gt_mode (Results 1 – 4 of 4) sorted by relevance
| /external/igt-gpu-tools/tools/ |
| D | intel_reg_checker.c | 152 uint32_t gt_mode; in check_gt_mode() local
158 gt_mode = read_and_print_reg("GT_MODE", 0x20d0); in check_gt_mode()
160 gt_mode = read_and_print_reg("GT_MODE", 0x7008); in check_gt_mode()
163 check_perf_bit(gt_mode, 8, "Full Rate Sampler Disable", false); in check_gt_mode()
170 check_bit(gt_mode, 6, in check_gt_mode()
173 check_perf_bit(gt_mode, 6, in check_gt_mode()
176 check_perf_bit(gt_mode, 5, "TD Four Row Dispatch Disable", in check_gt_mode()
178 check_perf_bit(gt_mode, 4, "Full Size URB Disable", false); in check_gt_mode()
179 check_perf_bit(gt_mode, 3, "Full Size SF FIFO Disable", false); in check_gt_mode()
180 check_perf_bit(gt_mode, 1, "VS Quad Thread Dispatch Disable", in check_gt_mode()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_misc_state.c | 678 const uint32_t gt_mode = in brw_emit_hashing_mode() local
687 brw_load_register_imm32(brw, GEN7_GT_MODE, gt_mode); in brw_emit_hashing_mode()
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_cmd_buffer.c | 5057 uint32_t gt_mode; in genX() local
5059 anv_pack_struct(>_mode, GENX(GT_MODE), in genX()
5069 emit_lri(&cmd_buffer->batch, GENX(GT_MODE_num), gt_mode); in genX()
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| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_state.c | 7755 uint32_t gt_mode; in genX() local
7757 iris_pack_state(GENX(GT_MODE), >_mode, reg) { in genX()
7770 iris_emit_lri(batch, GT_MODE, gt_mode); in genX()
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