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/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll279 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
287 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
295 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
303 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
327 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
335 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
375 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
383 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dalu64.ll279 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
287 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
295 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
303 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
327 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
335 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
375 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
383 %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll118 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
120 %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
125 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
127 %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
132 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
134 %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
139 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
141 %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll118 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
120 %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
125 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
127 %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
132 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
134 %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
139 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
141 %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
/external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/
Dmodernize-use-trailing-return-type.cpp461 WRAP(const) int& h16();
463 WRAP(CONST) int& h16();
466 CONCAT(con, st) int& h16();
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-scalar-recip.s9 frecps h21, h16, h13
Dneon-scalar-by-elem-saturating-mla.s8 sqdmlal s11, h16, v8.h[4]
/external/llvm/test/MC/AArch64/
Dneon-scalar-recip.s9 frecps h21, h16, h13
Dneon-scalar-by-elem-saturating-mla.s8 sqdmlal s11, h16, v8.h[4]
/external/capstone/suite/MC/AArch64/
Dneon-scalar-by-elem-saturating-mla.s.cs4 0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4]
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc495 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
505 __ Fadd(h4, h16, h18); in TEST()
506 __ Fadd(h5, h15, h16); in TEST()
507 __ Fadd(h6, h16, h15); in TEST()
587 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
596 __ Fsub(h4, h18, h16); in TEST()
598 __ Fsub(h6, h16, h16); in TEST()
678 __ Fmov(h16, kFP16NegativeInfinity); in TEST()
688 __ Fmul(h4, h16, h20); in TEST()
690 __ Fmul(h6, h19, h16); in TEST()
[all …]
Dtest-disasm-fp-aarch64.cc220 COMPARE(fccmp(h30, h16, NCFlag, pl), "fccmp h30, h16, #NzCv, pl"); in TEST()
236 COMPARE(fccmpe(h30, h16, NCFlag, pl), "fccmpe h30, h16, #NzCv, pl"); in TEST()
/external/XNNPACK/src/f16-gemm/gen/
D1x16-minmax-aarch64-neonfp16arith-ld32.S123 STR h16, [x6]
D1x8-minmax-aarch64-neonfp16arith-ld64.S125 STR h16, [x6]
D4x8-minmax-aarch64-neonfp16arith-ld64.S218 STR h16, [x6]
/external/XNNPACK/src/f16-gemm/gen-inc/
D1x8inc-minmax-aarch64-neonfp16arith-ld64.S128 STR h16, [x6]
D1x16inc-minmax-aarch64-neonfp16arith-ld32.S126 STR h16, [x6]
/external/mesa3d/src/gallium/auxiliary/rbug/
Drbug_texture.c288 uint16_t *h16, in rbug_send_texture_info_reply() argument
329 height[i] = h16[i]; in rbug_send_texture_info_reply()
/external/XNNPACK/src/f16-gemm/
D4x8-aarch64-neonfp16arith-ld64.S.in263 STR h16, [x6]
265 STR h16, [x6]
D4x16-aarch64-neonfp16arith-ld32.S.in268 STR h16, [x6]
270 STR h16, [x6]
D1x16-aarch64-neonfp16arith-ld32.S.in133 STR h16, [x6]
D1x8-aarch64-neonfp16arith-ld64.S.in135 STR h16, [x6]
/external/llvm/unittests/Support/
DYAMLIOTest.cpp256 Hex16 h16; member
280 io.mapRequired("h16", bt.h16); in mapping()
330 EXPECT_EQ(map.h16, Hex16(0x8765)); in TEST()
357 map.h16 = 50000; in TEST()
386 EXPECT_EQ(map.h16, Hex16(50000)); in TEST()
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Darith.ll410 ; CHECK-MVE1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h16 = shl <16 x i8> …
449 ; CHECK-MVE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h16 = shl <16 x i8> …
488 ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h16 = shl <16 x i8> …
527 ; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x…
566 ; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x…
605 ; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h16 = shl <16 x i8> u…
644 ; CHECK-MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h16 = shl <16 x …
682 %h16 = shl <16 x i8> undef, undef
723 ; CHECK-MVE1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h16 = shl <16 x i16>…
762 ; CHECK-MVE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h16 = shl <16 x i16>…
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-fadd.ll161 ; CHECKNOFP16-NEXT: mov h16, v1.h[3]
169 ; CHECKNOFP16-NEXT: fcvt s16, h16

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