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Searched refs:hasExtraDefRegAllocReq (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrDesc.h463 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
/external/llvm-project/llvm/utils/TableGen/
DInstrDocsEmitter.cpp132 FLAG(hasExtraDefRegAllocReq) in EmitInstrDocs()
DCodeGenInstruction.h270 bool hasExtraDefRegAllocReq : 1; variable
DInstrInfoEmitter.cpp778 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq) in emitRecord()
DCodeGenInstruction.cpp419 hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); in CodeGenInstruction()
/external/llvm-project/llvm/include/llvm/MC/
DMCInstrDesc.h539 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCInstrDesc.h554 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
/external/llvm/utils/TableGen/
DCodeGenInstruction.h252 bool hasExtraDefRegAllocReq : 1; variable
DInstrInfoEmitter.cpp505 if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; in emitRecord()
DCodeGenInstruction.cpp339 hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); in CodeGenInstruction()
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td248 let hasExtraDefRegAllocReq = 1 in
315 let hasExtraDefRegAllocReq = 1 in {
325 } // hasExtraDefRegAllocReq = 1
978 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
987 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1010 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1019 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td284 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
367 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
539 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
617 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
736 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
817 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td260 let hasExtraDefRegAllocReq = 1 in
327 let hasExtraDefRegAllocReq = 1 in {
337 } // hasExtraDefRegAllocReq = 1
1138 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
1147 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1170 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1179 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
/external/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp589 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
DAggressiveAntiDepBreaker.cpp371 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp614 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
DAggressiveAntiDepBreaker.cpp389 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
/external/llvm-project/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp611 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td280 let hasExtraDefRegAllocReq = 1 in
347 let hasExtraDefRegAllocReq = 1 in {
357 } // hasExtraDefRegAllocReq = 1
1283 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in {
1303 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1326 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h725 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td767 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
779 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
812 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
1530 hasExtraDefRegAllocReq = 1 in
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td804 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
816 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
849 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,
1716 hasExtraDefRegAllocReq = 1 in
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td816 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
828 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
861 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,
1728 hasExtraDefRegAllocReq = 1 in
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstr.h987 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
/external/llvm-project/llvm/include/llvm/CodeGen/
DMachineInstr.h1092 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {

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