| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstX86BaseImpl.h | 428 assert(Dest->hasReg()); in emit()
441 assert(Dest->hasReg()); in emitIAS()
593 if (Var->hasReg()) { in emitIAS()
655 if (Var->hasReg()) { in emitIAS()
713 if (Var->hasReg()) { in emitIASOpTyGPR()
737 assert(Var->hasReg()); in emitIASRegOpTyGPR()
742 if (SrcVar->hasReg()) { in emitIASRegOpTyGPR()
783 assert(SrcVar->hasReg()); in emitIASAddrOpTyGPR()
810 assert(!Op0Var->hasReg()); in emitIASAsAddrOpTyGPR()
833 assert(Var->hasReg()); in emitIASGPRShift()
[all …]
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| D | IceCfgNode.cpp | 374 if (!Var1->hasReg()) in sameVarOrReg()
376 if (!Var2->hasReg()) in sameVarOrReg()
525 if (Var->hasReg()) in advancedPhiLowering()
527 if (!Item.Dest->hasReg()) in advancedPhiLowering()
973 if (!Var->hasReg()) in emitRegisterUsage()
1012 if (!Instr->isDestRedefined() && Dest && Dest->hasReg()) in emitLiveRangesEnded()
1016 if (ShouldReport && Var->hasReg()) { in emitLiveRangesEnded()
1044 if (!Dest->hasReg()) in updateStats()
1049 if (!Src->hasReg()) in updateStats()
1109 if (DecorateAsm && Dest->hasReg()) { in emit()
[all …]
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| D | IceInstARM32.cpp | 1307 if (!Reg->hasReg()) { in validatePushOrPopRegisterListOrDie()
1389 assert(Before->hasReg()); in isAssignedConsecutiveRegisters()
1390 assert(After->hasReg()); in isAssignedConsecutiveRegisters()
1409 assert(Var->hasReg() && "stack op only applies to registers"); in emitUsingForm()
1434 assert(NextReg->hasReg()); in emitUsingForm()
1561 assert(Src->hasReg()); in getDRegister()
1618 assert(Src->hasReg()); in getSRegister()
1908 assert(DestHi->hasReg()); in emitMultiDestSingleSource()
1909 assert(DestLo->hasReg()); in emitMultiDestSingleSource()
1910 assert(Src->hasReg()); in emitMultiDestSingleSource()
[all …]
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| D | IceRegAlloc.cpp | 133 if (Var->hasReg()) { in initForGlobal()
226 if (Var->hasReg() || Var->mustHaveReg()) { in initForInfOnly()
235 (Var->hasReg() || Var->mustHaveReg())) { in initForInfOnly()
260 if (Var->hasReg()) { in initForInfOnly()
311 if (Var->hasReg()) { in initForSecondChance()
598 assert(Item->hasReg()); in filterFreeWithPrecoloredRanges()
865 if (Iter.Cur->hasReg()) { in scan()
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| D | IceInstX8632.cpp | 306 assert(!Var->hasReg()); in toAsmAddress()
317 assert(!Var->hasReg()); in emit()
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| D | IceInstX8664.cpp | 315 assert(!Var->hasReg()); in toAsmAddress()
326 assert(!Var->hasReg()); in emit()
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| D | IceOperand.cpp | 558 (!hasReg() && !Func->getTarget()->hasComputedFrame())) { in dump()
565 if (hasReg()) { in dump()
573 hasReg() ? getBaseRegNum() : Func->getTarget()->getFrameOrStackReg(); in dump()
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| D | IceVariableSplitting.cpp | 34 return !Var->hasReg() && Var->mayHaveReg(); in isAllocable()
41 return Var->hasReg() || Var->mustHaveReg(); in isInf()
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| D | IceInstMIPS32.cpp | 427 assert(RA->hasReg()); in emit()
612 assert(RA->hasReg()); in emitIAS()
639 const bool DestIsReg = Dest->hasReg(); in emit()
640 const bool SrcIsReg = (SrcV && SrcV->hasReg()); in emit()
696 const bool DestIsReg = Dest->hasReg(); in emitIAS()
697 const bool SrcIsReg = (SrcV && SrcV->hasReg()); in emitIAS()
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| D | IceLiveness.cpp | 105 (!IsFullInit && !Var->hasReg() && !Var->mustHaveReg())) in initInternal()
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| D | IceTargetLowering.cpp | 575 if (!Var->mustNotHaveReg() && !Var->hasReg()) { in postRegallocSplitting()
647 if (!ExtraVar->hasReg()) { in postRegallocSplitting()
801 if (Var->hasReg()) { in getVarStackSlotParams()
814 if (!Var->hasReg()) { in getVarStackSlotParams()
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| D | IceInst.cpp | 1090 if (Dest->hasReg() && Dest->getRegNum() == SrcVar->getRegNum()) { in checkForRedundantAssign()
1095 if (!Dest->hasReg() && !SrcVar->hasReg()) { in checkForRedundantAssign()
1110 if (SrcVar->hasReg() && Dest->hasStackOffset() && in checkForRedundantAssign()
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| D | IceOperand.h | 741 bool hasReg() const { return getRegNum().hasValue(); } in hasReg() function
745 assert(!hasReg() || RegNum == NewRegNum); in setRegNum()
828 if (!Root->hasReg() && Root->hasStackOffset()) { in getLinkedToStackRoot()
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| D | IceTargetLoweringX8664.cpp | 343 if (!Var->hasReg()) { in isAssignedToRspOrRbp()
464 if (T->hasReg()) { in _sandbox_mem_reference()
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| D | IceAssemblerMIPS32.cpp | 126 assert(Var->hasReg() && isScalarIntegerType(Var->getType())); in getEncodedGPRegNum()
132 assert(Var->hasReg() && isScalarFloatingType(Var->getType())); in getEncodedFPRegNum()
147 if (Var->hasReg()) { in encodeOperand()
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| D | IceTargetLoweringARM32.cpp | 401 assert(!Var64->hasReg() || Var64->mustHaveReg()); in copyRegAllocFromInfWeightVariable64On32()
402 if (!Var64->hasReg()) { in copyRegAllocFromInfWeightVariable64On32()
410 assert(Lo->hasReg() == Hi->hasReg()); in copyRegAllocFromInfWeightVariable64On32()
411 if (Lo->hasReg()) { in copyRegAllocFromInfWeightVariable64On32()
1225 if (Var->hasReg()) { in emitVariable()
1410 if (!Arg->hasReg()) { in finishArgumentLowering()
1866 if (!Dest->hasReg()) { in legalizeMov()
1868 assert(SrcR->hasReg()); in legalizeMov()
1894 if (!Var->hasReg()) { in legalizeMov()
3547 if (Dest->hasReg()) { in lowerAssign()
[all …]
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| D | IceTargetLoweringX8632.cpp | 264 Dest->hasReg() ? Dest in emitGetIP()
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| D | IceTargetLoweringMIPS32.cpp | 1140 if (Var->hasReg()) { in emitVariable()
1468 if (!Arg->hasReg()) { in finishArgumentLowering()
1869 if (Dest->hasReg() && SrcR->hasReg()) { in legalizeMov()
1957 if (!Dest->hasReg()) { in legalizeMov()
1959 assert(SrcR->hasReg()); in legalizeMov()
2024 if (!Var->hasReg()) { in legalizeMov()
3072 if (Dest->hasReg()) { in lowerAssign()
5863 !Subst->hasReg()) { in legalize()
5980 bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg()); in legalize()
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| D | IceAssemblerARM32.cpp | 179 assert(Var->hasReg()); in getEncodedGPRegNum()
186 assert(Var->hasReg()); in getEncodedSRegNum()
356 if (Var->hasReg()) { in encodeOperand()
486 if (Var->hasReg()) in encodeAddress()
492 Var->hasReg() ? Var->getBaseRegNum() : TInfo.FrameOrStackReg; in encodeAddress()
499 if (!Var->hasReg()) in encodeAddress()
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| D | IceTargetLoweringX86BaseImpl.h | 951 if (Var->hasReg()) {
982 if (Var->hasReg())
1082 assert(!Root->hasReg());
1083 if (!Root->hasReg()) {
1351 if (Arg->hasReg()) {
6786 if (Dest->hasReg()) {
7926 if (Subst->mustHaveReg() && !Subst->hasReg()) {
8039 bool MustHaveRegister = (Var->hasReg() || Var->mustHaveReg());
8109 if (Var->hasReg())
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| D | IceTargetLoweringX86Base.h | 197 assert(Dest->hasReg()); in createGetIPForRegister()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 129 bool hasReg() { return VGPR != AMDGPU::NoRegister;} in hasReg() function
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| D | SIRegisterInfo.cpp | 531 if (Spill.hasReg()) { in eliminateFrameIndex()
595 if (Spill.hasReg()) { in eliminateFrameIndex()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 439 bool hasReg() { return VGPR != 0;}
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 450 bool hasReg() { return VGPR != 0;}
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