Home
last modified time | relevance | path

Searched refs:hasSSE1 (Results 1 – 25 of 26) sorted by relevance

12

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86Subtarget.h584 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1() function
636 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); in hasSSEPrefetch()
DX86CallingConv.td103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
350 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
351 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
543 CCIfSubtarget<"hasSSE1()",
634 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
635 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
682 CCIfSubtarget<"hasSSE1()",
DX86RegisterInfo.cpp285 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
412 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
DX86FastISel.cpp66 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
486 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitStore()
1342 bool X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86ChooseCmpOpcode()
2156 !((Subtarget->hasSSE1() && RetVT == MVT::f32) || in X86FastEmitSSESelect()
2805 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2994 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3105 if (!Subtarget->hasSSE1()) in fastLowerArguments()
3466 assert((Subtarget->hasSSE1() || !NumXMMRegs) in fastLowerCall()
3561 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
DX86TargetTransformInfo.cpp121 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
139 if (ST->hasSSE1() && PreferVectorWidth >= 128) in getRegisterBitWidth()
867 if (ST->hasSSE1()) in getArithmeticInstrCost()
1266 if (ST->hasSSE1()) in getShuffleCost()
1877 if (ST->hasSSE1()) in getCmpSelInstrCost()
2255 if (ST->hasSSE1()) in getIntrinsicInstrCost()
2952 if (ST->hasSSE1()) in getMinMaxReductionCost()
2981 if (ST->hasSSE1()) in getMinMaxReductionCost()
3373 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); in isLegalNTLoad()
3398 return ST->hasSSE1(); in isLegalNTStore()
DX86LegalizerInfo.cpp285 if (!Subtarget.hasSSE1()) in setLegalizerInfoSSE1()
DX86ISelLowering.cpp114 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
682 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
838 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { in X86TargetLowering()
2235 if (Subtarget.hasSSE1()) in getByValTypeAlignment()
2280 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
2698 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
3020 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerCallResult()
3330 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1()) in get64BitArgumentXMMs()
3543 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) && in LowerFormalArguments()
4070 assert((Subtarget.hasSSE1() || !NumXMMRegs) in LowerCall()
[all …]
DX86InstrInfo.td849 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
850 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
938 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
/external/llvm-project/llvm/lib/Target/X86/
DX86Subtarget.h620 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1() function
679 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); in hasSSEPrefetch()
DX86CallingConv.td103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
353 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
354 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
549 CCIfSubtarget<"hasSSE1()",
640 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
641 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
688 CCIfSubtarget<"hasSSE1()",
DX86RegisterInfo.cpp280 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
407 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
DX86FastISel.cpp65 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
485 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitStore()
1358 bool X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86ChooseCmpOpcode()
2172 !((Subtarget->hasSSE1() && RetVT == MVT::f32) || in X86FastEmitSSESelect()
2825 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3013 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3124 if (!Subtarget->hasSSE1()) in fastLowerArguments()
3483 assert((Subtarget->hasSSE1() || !NumXMMRegs) in fastLowerCall()
3578 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
DX86LegalizerInfo.cpp280 if (!Subtarget.hasSSE1()) in setLegalizerInfoSSE1()
DX86TargetTransformInfo.cpp121 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
139 if (ST->hasSSE1() && PreferVectorWidth >= 128) in getRegisterBitWidth()
940 if (ST->hasSSE1()) in getArithmeticInstrCost()
1391 if (ST->hasSSE1()) in getShuffleCost()
2273 if (ST->hasSSE1()) in getCmpSelInstrCost()
2865 if (ST->hasSSE1()) in getTypeBasedIntrinsicInstrCost()
3680 if (ST->hasSSE1()) in getMinMaxCost()
4301 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); in isLegalNTLoad()
4326 return ST->hasSSE1(); in isLegalNTStore()
DX86ISelLowering.cpp108 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
691 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
847 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { in X86TargetLowering()
2250 if (Subtarget.hasSSE1()) in getByValTypeAlignment()
2283 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
2698 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
3028 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerCallResult()
3348 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1()) in get64BitArgumentXMMs()
3435 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) && in createVarArgAreaAndStoreRegisters()
4172 assert((Subtarget.hasSSE1() || !NumXMMRegs) in LowerCall()
[all …]
DX86InstrInfo.td875 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
876 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
965 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp245 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
344 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
DX86Subtarget.h382 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1() function
DX86FastISel.cpp66 X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86FastISel()
1330 bool X86ScalarSSEf32 = Subtarget->hasSSE1(); in X86ChooseCmpOpcode()
2065 !((Subtarget->hasSSE1() && RetVT == MVT::f32) || in X86FastEmitSSESelect()
2641 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2830 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2937 if (!Subtarget->hasSSE1()) in fastLowerArguments()
3274 assert((Subtarget->hasSSE1() || !NumXMMRegs) in fastLowerCall()
3360 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
DX86CallingConv.td332 CCIfSubtarget<"hasSSE1()",
467 CCIfSubtarget<"hasSSE1()",
DX86TargetTransformInfo.cpp45 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
60 if (ST->hasSSE1()) return 128; in getRegisterBitWidth()
DX86ISelLowering.cpp77 X86ScalarSSEf32 = Subtarget.hasSSE1(); in X86TargetLowering()
246 if (Subtarget.hasSSE1() && !Subtarget.hasSSE3()) in X86TargetLowering()
432 if (Subtarget.hasSSE1()) in X86TargetLowering()
719 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { in X86TargetLowering()
1786 if (Subtarget.hasSSE1()) in getByValTypeAlignment()
1826 if (Subtarget.hasSSE1()) in getOptimalMemOpType()
2108 (Subtarget.is64Bit() && !Subtarget.hasSSE1())) { in LowerReturn()
2299 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget.hasSSE1())) { in LowerCallResult()
2546 if (isSoftFloat || NoImplicitFloatOps || !Subtarget.hasSSE1()) in get64BitArgumentXMMs()
2729 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) && in LowerFormalArguments()
[all …]
DX86InstrInfo.td778 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
779 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
853 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc878 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
902 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1548 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1686 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1950 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1974 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2217 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2224 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2421 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2445 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
[all …]
DX86GenFastISel.inc847 if ((!Subtarget->hasSSE1())) {
882 if ((!Subtarget->hasSSE1())) {
977 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
990 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
1118 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
1121 if ((!Subtarget->hasSSE1())) {
1151 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
1712 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
1734 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
1952 if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) {
[all …]

12