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Searched refs:hevc_deblock (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_enc_2_0.c94 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_loop_filter_hevc()
95 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_loop_filter_hevc()
96 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_loop_filter_hevc()
97 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_loop_filter_hevc()
98 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_loop_filter_hevc()
99 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_loop_filter_hevc()
228 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
229 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
235 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
238 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
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Dradeon_vcn_enc_3_0.c143 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
144 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
150 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
153 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
155 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
156 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
157 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
Dradeon_uvd_enc_1_1.c358 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = in radeon_uvd_enc_deblocking_filter_hevc()
360 enc->enc_pic.hevc_deblock.deblocking_filter_disabled = in radeon_uvd_enc_deblocking_filter_hevc()
362 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_uvd_enc_deblocking_filter_hevc()
363 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; in radeon_uvd_enc_deblocking_filter_hevc()
364 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; in radeon_uvd_enc_deblocking_filter_hevc()
365 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; in radeon_uvd_enc_deblocking_filter_hevc()
368 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_uvd_enc_deblocking_filter_hevc()
369 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_uvd_enc_deblocking_filter_hevc()
370 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_uvd_enc_deblocking_filter_hevc()
371 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_uvd_enc_deblocking_filter_hevc()
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Dradeon_vcn_enc_1_2.c259 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_deblocking_filter_hevc()
260 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_deblocking_filter_hevc()
261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_hevc()
262 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_deblocking_filter_hevc()
263 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_hevc()
264 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_hevc()
517 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
518 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
524 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
527 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
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Dradeon_vcn_enc.c151 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = in radeon_vcn_enc_get_param()
153 enc->enc_pic.hevc_deblock.deblocking_filter_disabled = in radeon_vcn_enc_get_param()
155 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_vcn_enc_get_param()
156 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; in radeon_vcn_enc_get_param()
157 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; in radeon_vcn_enc_get_param()
158 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; in radeon_vcn_enc_get_param()
Dradeon_uvd_enc.h377 ruvd_enc_hevc_deblocking_filter_t hevc_deblock; member
Dradeon_vcn_enc.h460 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; member