| /external/igt-gpu-tools/assembler/ |
| D | gen8_instruction.c | 58 if (reg.hstride == BRW_HORIZONTAL_STRIDE_0) in gen8_set_dst()
59 reg.hstride = BRW_HORIZONTAL_STRIDE_1; in gen8_set_dst()
60 gen8_set_dst_da1_hstride(inst, reg.hstride); in gen8_set_dst()
73 if (reg.hstride == BRW_HORIZONTAL_STRIDE_0) in gen8_set_dst()
74 reg.hstride = BRW_HORIZONTAL_STRIDE_1; in gen8_set_dst()
75 gen8_set_dst_da1_hstride(inst, reg.hstride); in gen8_set_dst()
99 int width, hstride, vstride, execsize; in gen8_validate_reg() local
109 assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg)); in gen8_validate_reg()
110 hstride = hstride_for_reg[reg.hstride]; in gen8_validate_reg()
131 if (execsize == width && hstride != 0) { in gen8_validate_reg()
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| D | brw_eu_debug.c | 63 hwreg.hstride == BRW_HORIZONTAL_STRIDE_1 && in brw_print_reg()
71 hwreg.hstride == BRW_HORIZONTAL_STRIDE_0 && in brw_print_reg()
86 hwreg.hstride ? (1<<(hwreg.hstride-1)) : 0, in brw_print_reg()
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| D | brw_reg.h | 121 unsigned hstride:2; /* align1 only */ member
186 unsigned hstride, in brw_reg() argument
206 reg.hstride = hstride; in brw_reg()
431 imm.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_imm_v()
443 imm.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_imm_vf()
458 imm.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_imm_vf4()
605 stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride) in stride() argument
609 reg.hstride = cvt(hstride); in stride()
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| D | gram.y | 74 .hstride = 1,
314 int width, hstride, vstride, execsize; in validate_src_reg() local
332 assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg)); in validate_src_reg()
333 hstride = hstride_for_reg[reg.hstride]; in validate_src_reg()
353 if (execsize == width && hstride != 0) { in validate_src_reg()
354 if (vstride != -1 && vstride != width * hstride) in validate_src_reg()
365 if (width == 1 && hstride != 0) in validate_src_reg()
367 " (should be 0)\n", hstride); in validate_src_reg()
372 if (hstride != 0) in validate_src_reg()
374 "horizontal stride is %d (should be 0)\n", hstride); in validate_src_reg()
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| D | brw_eu_emit.c | 123 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) in brw_set_dest()
124 dest.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_set_dest()
125 insn->bits1.da1.dest_horiz_stride = dest.hstride; in brw_set_dest()
141 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) in brw_set_dest()
142 dest.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_set_dest()
143 insn->bits1.ia1.dest_horiz_stride = dest.hstride; in brw_set_dest()
167 int width, hstride, vstride, execsize; in validate_reg() local
186 assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg)); in validate_reg()
187 hstride = hstride_for_reg[reg.hstride]; in validate_reg()
213 if (execsize == width && hstride != 0) { in validate_reg()
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| /external/webp/src/dsp/ |
| D | dec_mips32.c | 93 int hstride, int vstride, int size, in FilterLoop26() argument
97 if (needs_filter2(p, hstride, thresh2, ithresh)) { in FilterLoop26()
98 if (hev(p, hstride, hev_thresh)) { in FilterLoop26()
99 do_filter2(p, hstride); in FilterLoop26()
101 do_filter6(p, hstride); in FilterLoop26()
109 int hstride, int vstride, int size, in FilterLoop24() argument
113 if (needs_filter2(p, hstride, thresh2, ithresh)) { in FilterLoop24()
114 if (hev(p, hstride, hev_thresh)) { in FilterLoop24()
115 do_filter2(p, hstride); in FilterLoop24()
117 do_filter4(p, hstride); in FilterLoop24()
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| D | dec.c | 595 int hstride, int vstride, int size, in FilterLoop26_C() argument
600 if (NeedsFilter2_C(p, hstride, thresh2, ithresh)) { in FilterLoop26_C()
601 if (Hev(p, hstride, hev_thresh)) { in FilterLoop26_C()
602 DoFilter2_C(p, hstride); in FilterLoop26_C()
604 DoFilter6_C(p, hstride); in FilterLoop26_C()
612 int hstride, int vstride, int size, in FilterLoop24_C() argument
617 if (NeedsFilter2_C(p, hstride, thresh2, ithresh)) { in FilterLoop24_C()
618 if (Hev(p, hstride, hev_thresh)) { in FilterLoop24_C()
619 DoFilter2_C(p, hstride); in FilterLoop24_C()
621 DoFilter4_C(p, hstride); in FilterLoop24_C()
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| D | dec_mips_dsp_r2.c | 161 int hstride, int vstride, int size, in FilterLoop26() argument
291 : [hstride]"r"(hstride), [thresh2]"r"(thresh2), in FilterLoop26()
299 int hstride, int vstride, int size, in FilterLoop24() argument
421 [hev_thresh]"r"(hev_thresh), [hstride]"r"(hstride), in FilterLoop24()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_eu_validate.c | 587 is_packed(unsigned vstride, unsigned width, unsigned hstride) in is_packed() argument
591 return hstride == 0; in is_packed()
593 return hstride == 1; in is_packed()
979 unsigned vstride, width, hstride, element_size, subreg; in general_restrictions_on_region_parameters() local
989 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \ in general_restrictions_on_region_parameters()
1016 if (exec_size == width && hstride != 0) { in general_restrictions_on_region_parameters()
1017 ERROR_IF(vstride != width * hstride, in general_restrictions_on_region_parameters()
1026 ERROR_IF(hstride != 0, in general_restrictions_on_region_parameters()
1033 ERROR_IF(vstride != 0 || hstride != 0, in general_restrictions_on_region_parameters()
1041 if (vstride == 0 && hstride == 0) { in general_restrictions_on_region_parameters()
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| D | brw_reg.h | 238 unsigned hstride:2; /* align1 only */ member
411 unsigned hstride, in brw_reg() argument
445 reg.hstride = hstride; in brw_reg()
758 imm.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_imm_vf4()
988 stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride) in stride() argument
992 reg.hstride = cvt(hstride); in stride()
1006 if (reg.hstride) in spread()
1007 reg.hstride += cvt(s) - 1; in spread()
1236 reg.hstride == h; in region_matches()
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| D | brw_ir_fs.h | 124 const unsigned stride = reg.hstride ? 1 << (reg.hstride - 1) : 0; in horiz_offset()
197 r.hstride == 0 ? 0 : in reg_padding()
198 1 << (r.hstride - 1)); in reg_padding()
261 const unsigned period = (reg.hstride == 0 && reg.vstride == 0 ? 1 : in is_periodic()
302 reg.hstride += (reg.hstride ? delta : 0); in subscript()
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| D | brw_eu_emit.c | 106 dest.hstride == BRW_HORIZONTAL_STRIDE_1) { in brw_set_dest()
107 dest.hstride = BRW_HORIZONTAL_STRIDE_2; in brw_set_dest()
120 (dest.hstride == BRW_HORIZONTAL_STRIDE_1 && in brw_set_dest()
133 assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1 && in brw_set_dest()
148 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) in brw_set_dest()
149 dest.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_set_dest()
150 brw_inst_set_dst_hstride(devinfo, inst, dest.hstride); in brw_set_dest()
172 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0) in brw_set_dest()
173 dest.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_set_dest()
174 brw_inst_set_dst_hstride(devinfo, inst, dest.hstride); in brw_set_dest()
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| D | brw_fs_generator.cpp | 133 assert(brw_reg.hstride == BRW_HORIZONTAL_STRIDE_1); in brw_reg_from_fs_reg()
144 assert(brw_reg.hstride > BRW_HORIZONTAL_STRIDE_1); in brw_reg_from_fs_reg()
145 brw_reg.hstride--; in brw_reg_from_fs_reg()
178 brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) { in brw_reg_from_fs_reg()
180 brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1; in brw_reg_from_fs_reg()
622 if ((src.vstride == 0 && src.hstride == 0) || in generate_shuffle()
690 assert(src.vstride == src.hstride + src.width); in generate_shuffle()
693 src.hstride - 1)); in generate_shuffle()
724 assert(dst.hstride == 1); in generate_shuffle()
731 brw_MOV(p, suboffset(dst, group * dst.hstride), in generate_shuffle()
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| D | brw_ir.h | 80 using brw_reg::hstride;
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| D | brw_fs_copy_propagation.cpp | 627 inst->src[arg].hstride = cvt(inst->src[arg].stride); in try_copy_propagate()
628 inst->src[arg].vstride = inst->src[arg].hstride + inst->src[arg].width; in try_copy_propagate()
630 inst->src[arg].vstride = inst->src[arg].hstride = in try_copy_propagate()
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| D | brw_vec4_generator.cpp | 937 offset.hstride == BRW_HORIZONTAL_STRIDE_1) { in generate_tes_add_indirect_urb_offset()
1920 src[0].hstride = BRW_HORIZONTAL_STRIDE_0; in generate_code()
1991 dst.hstride = BRW_HORIZONTAL_STRIDE_1; in generate_code()
2016 dst.hstride = BRW_HORIZONTAL_STRIDE_2; in generate_code()
2048 src[0].hstride = BRW_HORIZONTAL_STRIDE_0; in generate_code()
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| D | brw_disasm.c | 1033 hstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride) in hstride_from_align1_3src_hstride() argument
1035 switch (hstride) { in hstride_from_align1_3src_hstride()
1046 vstride_from_align1_3src_hstride(enum gen10_align1_3src_src_horizontal_stride hstride) in vstride_from_align1_3src_hstride() argument
1048 switch (hstride) { in vstride_from_align1_3src_hstride()
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| D | test_eu_validate.cpp | 2833 unsigned hstride; in TEST_P() member
2903 brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); in TEST_P()
2911 brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); in TEST_P()
2914 brw_inst_set_src1_hstride(&devinfo, last_inst, inst[i].srcs[1].hstride); in TEST_P()
2922 brw_inst_set_3src_a1_src0_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); in TEST_P()
2924 brw_inst_set_3src_a1_src1_hstride(&devinfo, last_inst, inst[i].srcs[0].hstride); in TEST_P()
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| D | brw_fs_builder.h | 754 src.hstride != BRW_HORIZONTAL_STRIDE_1) in fix_3src_operand()
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| D | brw_fs.cpp | 545 return hstride == BRW_HORIZONTAL_STRIDE_1 && in is_contiguous()
546 vstride == width + hstride; in is_contiguous()
564 hstride == 0 ? 0 : in component_size()
565 1 << (hstride - 1)); in component_size()
7403 unsigned hstride = inst->src[i].hstride; in dump_instruction() local
7404 stride = (hstride == 0 ? 0 : (1 << (hstride - 1))); in dump_instruction()
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| D | brw_vec4.cpp | 2092 src.vstride = src.width + src.hstride; in convert_to_hw_regs()
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| /external/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 1510 $$.hstride = $2;
1522 $$.hstride = $2;
1536 $$.hstride = $2;
1543 $$.hstride = 1;
1641 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1672 $$.hstride = $2.hstride;
1687 $2.hstride,
1696 $$.hstride = $2.hstride;
1724 $4.hstride,
1753 $4.hstride,
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| /external/mesa3d/docs/relnotes/ |
| D | 19.0.4.rst | 124 hstride value.
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| D | 7.10.rst | 1195 hstride == 1.
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| D | 20.0.0.rst | 1526 - intel/compiler: Don't change hstride if not needed
|