Searched refs:hw_state (Results 1 – 3 of 3) sorted by relevance
67 ves->hw_state.attribs[i].binding = binding; in zink_create_vertex_elements_state()68 ves->hw_state.attribs[i].location = i; // TODO: unsure in zink_create_vertex_elements_state()69 ves->hw_state.attribs[i].format = zink_get_format(screen, in zink_create_vertex_elements_state()71 assert(ves->hw_state.attribs[i].format != VK_FORMAT_UNDEFINED); in zink_create_vertex_elements_state()72 ves->hw_state.attribs[i].offset = elem->src_offset; in zink_create_vertex_elements_state()75 ves->hw_state.num_bindings = num_bindings; in zink_create_vertex_elements_state()76 ves->hw_state.num_attribs = num_elements; in zink_create_vertex_elements_state()90 state->element_state = &ctx->element_state->hw_state; in zink_bind_vertex_elements_state()340 cso->hw_state.depth_test = VK_TRUE; in zink_create_depth_stencil_alpha_state()341 cso->hw_state.depth_compare_op = compare_op(depth_stencil_alpha->depth.func); in zink_create_depth_stencil_alpha_state()[all …]
43 struct zink_vertex_elements_hw_state hw_state; member59 struct zink_rasterizer_hw_state hw_state; member90 struct zink_depth_stencil_alpha_hw_state hw_state; member
141 for (unsigned i = 0; i < elems->hw_state.num_bindings; i++) { in zink_bind_vertex_buffers()155 if (elems->hw_state.num_bindings > 0) in zink_bind_vertex_buffers()157 elems->hw_state.num_bindings, in zink_bind_vertex_buffers()439 if (line_width_needed(reduced_prim, rast_state->hw_state.polygon_mode)) { in zink_draw_vbo()