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/external/llvm-project/llvm/test/CodeGen/Generic/
Dadd-with-overflow-24.ll6 define i1 @func1(i24 signext %v1, i24 signext %v2) nounwind {
8 %t = call {i24, i1} @llvm.sadd.with.overflow.i24(i24 %v1, i24 %v2)
9 %sum = extractvalue {i24, i1} %t, 0
10 %sum32 = sext i24 %sum to i32
11 %obit = extractvalue {i24, i1} %t, 1
23 define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
25 %t = call {i24, i1} @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)
26 %sum = extractvalue {i24, i1} %t, 0
27 %sum32 = zext i24 %sum to i32
28 %obit = extractvalue {i24, i1} %t, 1
[all …]
/external/llvm/test/CodeGen/Generic/
Dadd-with-overflow-24.ll6 define i1 @func1(i24 signext %v1, i24 signext %v2) nounwind {
8 %t = call {i24, i1} @llvm.sadd.with.overflow.i24(i24 %v1, i24 %v2)
9 %sum = extractvalue {i24, i1} %t, 0
10 %sum32 = sext i24 %sum to i32
11 %obit = extractvalue {i24, i1} %t, 1
23 define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
25 %t = call {i24, i1} @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)
26 %sum = extractvalue {i24, i1} %t, 0
27 %sum32 = zext i24 %sum to i32
28 %obit = extractvalue {i24, i1} %t, 1
[all …]
/external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/
Dlibatomic.ll10 define i24 @odd_sized_load(i24* %ptr) sanitize_memory {
11 ; CHECK: @odd_sized_load(i24* {{.*}}[[PTR:%.+]])
12 ; CHECK: [[VAL_PTR:%.*]] = alloca i24, align 1
14 ; CHECK: [[VAL_PTR_I8:%.*]] = bitcast i24* [[VAL_PTR]] to i8*
15 ; CHECK: [[PTR_I8:%.*]] = bitcast i24* [[PTR]] to i8*
38 ; CHECK: [[VAL:%.*]] = load i24, i24* [[VAL_PTR]]
39 ; CHECK: ret i24 [[VAL]]
40 %val_ptr = alloca i24, align 1
41 %val_ptr_i8 = bitcast i24* %val_ptr to i8*
42 %ptr_i8 = bitcast i24* %ptr to i8*
[all …]
Dcheck-array.ll7 define noundef [2 x i24] @check_array([2 x i24]* %p) sanitize_memory {
8 ; CHECK: @check_array([2 x i24]* [[P:%.*]])
9 ; CHECK: [[O:%.*]] = load [2 x i24], [2 x i24]* [[P]]
10 %o = load [2 x i24], [2 x i24]* %p
11 ; CHECK: [[FIELD0:%.+]] = extractvalue [2 x i24] %_msld, 0
12 ; CHECK: [[FIELD1:%.+]] = extractvalue [2 x i24] %_msld, 1
13 ; CHECK: [[F1_OR:%.+]] = or i24 [[FIELD0]], [[FIELD1]]
14 ; CHECK: %_mscmp = icmp ne i24 [[F1_OR]], 0
17 ; CHECK: ret [2 x i24] [[O]]
18 ret [2 x i24] %o
/external/llvm-project/llvm/test/CodeGen/X86/
Dwiden_bitops-0.ll6 ; AND/XOR/OR i24 as v3i8
9 define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind {
21 %1 = bitcast i24 %a to <3 x i8>
22 %2 = bitcast i24 %b to <3 x i8>
24 %4 = bitcast <3 x i8> %3 to i24
25 ret i24 %4
28 define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind {
40 %1 = bitcast i24 %a to <3 x i8>
41 %2 = bitcast i24 %b to <3 x i8>
43 %4 = bitcast <3 x i8> %3 to i24
[all …]
Dillegal-bitfield-loadstore.ll5 define void @i24_or(i24* %a) {
28 %aa = load i24, i24* %a, align 1
29 %b = or i24 %aa, 384
30 store i24 %b, i24* %a, align 1
34 define void @i24_and_or(i24* %a) {
59 %b = load i24, i24* %a, align 1
60 %c = and i24 %b, -128
61 %d = or i24 %c, 384
62 store i24 %d, i24* %a, align 1
66 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
[all …]
Dpr26835.ll7 define i24 @foo(i24 %a, i24 %b) {
8 %r = urem i24 %a, %b
9 ret i24 %r
Dpr35761.ll6 @z = global i24 0, align 4
30 %bf.load = load i24, i24* @z, align 4
31 %2 = zext i8 %conv3 to i24
32 %bf.value = and i24 %2, 4194303
33 store i24 %bf.value, i24* @z, align 2
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsdivrem24.ll57 %num.i24.0 = shl i32 %num, 8
58 %den.i24.0 = shl i32 %den, 8
59 %num.i24 = ashr i32 %num.i24.0, 8
60 %den.i24 = ashr i32 %den.i24.0, 8
61 %result = sdiv i32 %num.i24, %den.i24
76 %num.i24.0 = shl i32 %num, 7
77 %den.i24.0 = shl i32 %den, 7
78 %num.i24 = ashr i32 %num.i24.0, 7
79 %den.i24 = ashr i32 %den.i24.0, 7
80 %result = sdiv i32 %num.i24, %den.i24
[all …]
Dudivrem24.ll131 %num.i24.0 = shl i32 %num, 8
132 %den.i24.0 = shl i32 %den, 8
133 %num.i24 = lshr i32 %num.i24.0, 8
134 %den.i24 = lshr i32 %den.i24.0, 8
135 %result = udiv i32 %num.i24, %den.i24
149 %den.i24.0 = shl i32 %den, 8
151 %den.i24 = lshr i32 %den.i24.0, 8
152 %result = udiv i32 %num.i23, %den.i24
165 %num.i24.0 = shl i32 %num, 8
167 %num.i24 = lshr i32 %num.i24.0, 8
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dsdivrem24.ll57 %num.i24.0 = shl i32 %num, 8
58 %den.i24.0 = shl i32 %den, 8
59 %num.i24 = ashr i32 %num.i24.0, 8
60 %den.i24 = ashr i32 %den.i24.0, 8
61 %result = sdiv i32 %num.i24, %den.i24
76 %num.i24.0 = shl i32 %num, 7
77 %den.i24.0 = shl i32 %den, 7
78 %num.i24 = ashr i32 %num.i24.0, 7
79 %den.i24 = ashr i32 %den.i24.0, 7
80 %result = sdiv i32 %num.i24, %den.i24
[all …]
Dudivrem24.ll74 %num.i24.0 = shl i32 %num, 8
75 %den.i24.0 = shl i32 %den, 8
76 %num.i24 = lshr i32 %num.i24.0, 8
77 %den.i24 = lshr i32 %den.i24.0, 8
78 %result = udiv i32 %num.i24, %den.i24
92 %den.i24.0 = shl i32 %den, 8
94 %den.i24 = lshr i32 %den.i24.0, 8
95 %result = udiv i32 %num.i23, %den.i24
108 %num.i24.0 = shl i32 %num, 8
110 %num.i24 = lshr i32 %num.i24.0, 8
[all …]
/external/llvm/test/CodeGen/X86/
Dwiden_bitops-0.ll6 ; AND/XOR/OR i24 as v3i8
9 define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind {
21 %1 = bitcast i24 %a to <3 x i8>
22 %2 = bitcast i24 %b to <3 x i8>
24 %4 = bitcast <3 x i8> %3 to i24
25 ret i24 %4
28 define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind {
40 %1 = bitcast i24 %a to <3 x i8>
41 %2 = bitcast i24 %b to <3 x i8>
43 %4 = bitcast <3 x i8> %3 to i24
[all …]
Dpr26835.ll7 define i24 @foo(i24 %a, i24 %b) {
8 %r = urem i24 %a, %b
9 ret i24 %r
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-load-memory-metadata.mir6 define i32 @widen_load_range0_tbaa(i24 addrspace(1)* %ptr) {
7 %load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
8 %zext = zext i24 %load to i32
12 define i32 @widen_load_range1_tbaa(i24 addrspace(1)* %ptr) {
13 %load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
14 %zext = zext i24 %load to i32
18 define i32 @widen_load_tbaa0(i24 addrspace(1)* %ptr) {
19 %load = load i24, i24 addrspace(1)* %ptr, !tbaa !1
20 %zext = zext i24 %load to i32
24 define i32 @widen_load_tbaa1(i24 addrspace(1)* %ptr) {
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dinfinite-loop-postdom.ll8 define void @test1(i24 %a, i24 %b) {
13 %f = icmp uge i24 %a, %b
17 %x = add i24 %a, %b
25 define void @test1-canonicalized(i24 %a, i24 %b) {
30 %f.not = icmp ult i24 %a, %b
34 %x = add i24 %a, %b
44 define void @test2(i24 %a, i24 %b) {
49 %f = icmp uge i24 %a, %b
56 %x = add i24 %a, %b
61 define void @test2-canonicalized(i24 %a, i24 %b) {
[all …]
/external/llvm-project/compiler-rt/test/msan/
Dlibatomic_load_exceptions.cpp12 } i24; typedef
14 void copy(i24 *dst, i24 *src);
17 i24 uninit; in main()
18 i24 init = {0}; in main()
25 void copy(i24 *dst, i24 *src) { in copy()
Dlibatomic.c14 } i24; typedef
16 void copy(i24 *dst, i24 *src);
19 i24 uninit; in main()
20 i24 init = {0}; in main()
27 void copy(i24 *dst, i24 *src) { in copy()
/external/llvm/test/Transforms/SROA/
Dbig-endian.ll6 ; We fully promote these to the i24 load or store size, resulting in just masks
24 %aiptr = bitcast [3 x i8]* %a to i24*
25 %ai = load i24, i24* %aiptr
28 ; CHECK: %[[ext2:.*]] = zext i8 0 to i24
29 ; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
30 ; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
31 ; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
33 ; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
[all …]
/external/llvm-project/llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/
Dexpand-masked-load.ll66 define <2 x i24> @scalarize_v2i24(<2 x i24>* %p, <2 x i1> %mask, <2 x i24> %passthru) {
68 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i24>* [[P:%.*]] to i24*
74 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i24, i24* [[TMP1]], i32 0
75 ; CHECK-NEXT: [[TMP5:%.*]] = load i24, i24* [[TMP4]], align 1
76 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i24> [[PASSTHRU:%.*]], i24 [[TMP5]], i64 0
79 ; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i24> [ [[TMP6]], [[COND_LOAD]] ], [ [[PASSTHRU]], …
84 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i24, i24* [[TMP1]], i32 1
85 ; CHECK-NEXT: [[TMP10:%.*]] = load i24, i24* [[TMP9]], align 1
86 ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i24> [[RES_PHI_ELSE]], i24 [[TMP10]], i64 1
89 ; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i24> [ [[TMP11]], [[COND_LOAD1]] ], [ [[RES_PHI_E…
[all …]
/external/llvm-project/llvm/test/Transforms/ScalarizeMaskedMemIntrin/X86/
Dexpand-masked-load.ll65 define <2 x i24> @scalarize_v2i24(<2 x i24>* %p, <2 x i1> %mask, <2 x i24> %passthru) {
67 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i24>* [[P:%.*]] to i24*
73 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i24, i24* [[TMP1]], i32 0
74 ; CHECK-NEXT: [[TMP5:%.*]] = load i24, i24* [[TMP4]], align 1
75 ; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i24> [[PASSTHRU:%.*]], i24 [[TMP5]], i64 0
78 ; CHECK-NEXT: [[RES_PHI_ELSE:%.*]] = phi <2 x i24> [ [[TMP6]], [[COND_LOAD]] ], [ [[PASSTHRU]], …
83 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i24, i24* [[TMP1]], i32 1
84 ; CHECK-NEXT: [[TMP10:%.*]] = load i24, i24* [[TMP9]], align 1
85 ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i24> [[RES_PHI_ELSE]], i24 [[TMP10]], i64 1
88 ; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i24> [ [[TMP11]], [[COND_LOAD1]] ], [ [[RES_PHI_E…
[all …]
/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dfast-isel-i24.ll5 ; Test that fast-isel properly copes with i24 arguments and return types.
16 define i24 @add(i24 %x, i24 %y) {
17 %z = add i24 %x, %y
18 ret i24 %z
25 define i24 @return_zero() {
26 ret i24 0
/external/llvm-project/llvm/test/Transforms/SROA/
Dbig-endian.ll6 ; We fully promote these to the i24 load or store size, resulting in just masks
24 %aiptr = bitcast [3 x i8]* %a to i24*
25 %ai = load i24, i24* %aiptr
28 ; CHECK: %[[ext2:.*]] = zext i8 0 to i24
29 ; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
30 ; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
31 ; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
33 ; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dillegal-bitfield-loadstore.ll5 define void @i24_or(i24* %a) {
23 %aa = load i24, i24* %a, align 1
24 %b = or i24 %aa, 384
25 store i24 %b, i24* %a, align 1
29 define void @i24_and_or(i24* %a) {
46 %b = load i24, i24* %a, align 1
47 %c = and i24 %b, -128
48 %d = or i24 %c, 384
49 store i24 %d, i24* %a, align 1
53 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvec-trunc2.ll169 %i11 = trunc i32 %i1 to i24
170 %i21 = trunc i32 %i2 to i24
171 %i31 = trunc i32 %i3 to i24
172 %i41 = trunc i32 %i4 to i24
173 %i51 = trunc i32 %i5 to i24
174 %i61 = trunc i32 %i6 to i24
175 %i71 = trunc i32 %i7 to i24
176 %i81 = trunc i32 %i8 to i24
177 %v10 = insertelement <8 x i24> undef, i24 %i11, i32 0
178 %v11 = insertelement <8 x i24> %v10, i24 %i21, i32 1
[all …]

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