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Searched refs:i4_part_mask (Results 1 – 14 of 14) sorted by relevance

/external/libhevc/encoder/
Dhme_search_algo.c145 pf_sad_fxn = hme_get_sad_fxn(e_blk_size, ps_err_prms->i4_grid_mask, ps_err_prms->i4_part_mask); in hme_compute_grid_results()
148 hme_get_result_fxn(ps_err_prms->i4_grid_mask, ps_err_prms->i4_part_mask, i4_num_results); in hme_compute_grid_results()
205 S32 i4_part_mask, i4_grid_mask; in hme_pred_search_square_stepn() local
263 i4_part_mask = ps_search_prms->i4_part_mask; in hme_pred_search_square_stepn()
270 hme_create_valid_part_ids(i4_part_mask, ai4_valid_part_ids); in hme_pred_search_square_stepn()
278 s_err_prms.i4_part_mask = i4_part_mask; in hme_pred_search_square_stepn()
288 s_result_prms.i4_part_mask = ps_search_prms->i4_part_mask; in hme_pred_search_square_stepn()
364 ASSERT((ps_err_prms->i4_part_mask == 4) || (ps_err_prms->i4_part_mask == 16)); in hme_pred_search_square_stepn()
413 ASSERT((ps_err_prms->i4_part_mask == 4) || (ps_err_prms->i4_part_mask == 16)); in hme_pred_search_square_stepn()
501 S32 i4_part_mask, i4_grid_mask; in hme_pred_search() local
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Dihevce_me_instr_set_router.c319 S08 i1_grid_flag, U08 u1_is_cu_noisy, S32 i4_part_mask, S32 num_parts, S32 num_results) in hme_get_calc_sad_and_result_fxn() argument
327 [(!!(i4_part_mask & (ENABLE_SMP | ENABLE_NxN)) && in hme_get_calc_sad_and_result_fxn()
328 !(i4_part_mask & ENABLE_AMP)) in hme_get_calc_sad_and_result_fxn()
329 ? (!!(i4_part_mask & ENABLE_NxN) ? 0 : 1) in hme_get_calc_sad_and_result_fxn()
330 : (!!(i4_part_mask & ENABLE_AMP) ? 2 : 3)][num_parts - 1]; in hme_get_calc_sad_and_result_fxn()
380 PF_SAD_FXN_T hme_get_sad_fxn(BLK_SIZE_T e_blk_size, S32 i4_grid_mask, S32 i4_part_mask) in hme_get_sad_fxn() argument
386 if(i4_part_mask & (i4_part_mask - 1)) in hme_get_sad_fxn()
404 if(i4_part_mask & (i4_part_mask - 1)) in hme_get_sad_fxn()
Dhme_fullpel.c134 i4_temp_part_mask = ps_search_prms->i4_part_mask; in hme_fullpel_cand_sifter()
135 ps_search_prms->i4_part_mask &= ((ENABLE_2Nx2N) | (ENABLE_NxN)); in hme_fullpel_cand_sifter()
138 (ps_search_prms->i4_part_mask) & ((ENABLE_2Nx2N) | (ENABLE_NxN)), in hme_fullpel_cand_sifter()
188 ps_search_prms->i4_part_mask = i4_temp_part_mask; in hme_fullpel_cand_sifter()
191 ps_search_prms->i4_part_mask, &ps_fullpel_refine_ctxt->ai4_part_id[0]); in hme_fullpel_cand_sifter()
Dhme_utils.c475 (ps_search_results->i4_part_mask & ENABLE_NxN)) in hme_map_mvs_to_grid()
579 S32 hme_create_valid_part_ids(S32 i4_part_mask, S32 *pi4_valid_part_ids) in hme_create_valid_part_ids() argument
584 if(i4_part_mask & (1 << i)) in hme_create_valid_part_ids()
1016 void hme_reset_search_results(search_results_t *ps_search_results, S32 i4_part_mask, S32 mv_res) in hme_reset_search_results() argument
1024 ps_search_results->i4_part_mask = i4_part_mask; in hme_reset_search_results()
1037 if(!(i4_part_mask & (1 << i))) in hme_reset_search_results()
2277 S32 i4_part_mask) in hme_tu_recur_cand_harvester() argument
2287 if(i4_part_mask & ENABLE_2Nx2N) in hme_tu_recur_cand_harvester()
2295 if(!ps_inter_ctb_prms->i4_bidir_enabled || (i4_part_mask == ENABLE_2Nx2N)) in hme_tu_recur_cand_harvester()
2346 if(!(i4_part_mask & gai4_part_type_to_part_mask[j + start_part_type])) in hme_tu_recur_cand_harvester()
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Dihevce_me_instr_set_router.h171 BLK_SIZE_T e_blk_size, S32 i4_grid_mask, S32 i4_part_mask);
179 U08 u1_is_cu_noisy, S32 i4_part_mask, S32 num_parts, S32 num_results);
Dhme_subpel.c935 s_err_prms.i4_part_mask = (ENABLE_2Nx2N); in hme_compute_pred_and_evaluate_bi()
2182 S32 i4_part_mask, in hme_get_calc_sad_and_result_subpel_fxn() argument
2218 else if(((i4_part_mask & ENABLE_SQUARE_PARTS) != 0) && (u1_num_parts == 5)) in hme_get_calc_sad_and_result_subpel_fxn()
2262 else if(((i4_part_mask & ENABLE_SQUARE_PARTS) != 0) && (u1_num_parts == 5)) in hme_get_calc_sad_and_result_subpel_fxn()
2293 S32 i4_part_mask, in hme_subpel_refine_search_node_high_speed() argument
2366 i4_part_mask, in hme_subpel_refine_search_node_high_speed()
2403 s_result_prms.i4_part_mask = i4_part_mask; in hme_subpel_refine_search_node_high_speed()
2431 s_err_prms.i4_part_mask = (ENABLE_2Nx2N); in hme_subpel_refine_search_node_high_speed()
2913 S32 i4_part_mask, in hme_subpel_refine_search_node_high_speed() argument
3024 s_result_prms.i4_part_mask = i4_part_mask; in hme_subpel_refine_search_node_high_speed()
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Dhme_coarse.c1128 s_search_prms_8x4.i4_part_mask = (1 << PART_ID_2NxN_B); in hme_coarsest()
1137 s_search_prms_4x8.i4_part_mask = (1 << PART_ID_Nx2N_R); in hme_coarsest()
1143 s_search_prms_4x4.i4_part_mask = (1 << PART_ID_2Nx2N); in hme_coarsest()
1285 s_search_prms_8x4.i4_part_mask | s_search_prms_4x8.i4_part_mask, in hme_coarsest()
Dhme_utils.h174 S32 hme_create_valid_part_ids(S32 i4_part_mask, S32 *pi4_valid_part_ids);
355 void hme_reset_search_results(search_results_t *ps_search_results, S32 i4_part_mask, S32 mv_res);
Dhme_refine.c603 S32 i4_part_mask = ps_search_results->i4_part_mask; in hme_pick_eval_merge_candts() local
788 i4_part_mask = ps_search_results->i4_part_mask; in hme_pick_eval_merge_candts()
818 i4_num_valid_parts = hme_create_valid_part_ids(i4_part_mask, ai4_valid_part_ids); in hme_pick_eval_merge_candts()
825 s_result_prms.i4_part_mask = i4_part_mask; in hme_pick_eval_merge_candts()
832 s_err_prms.i4_part_mask = (ENABLE_2Nx2N); in hme_pick_eval_merge_candts()
925 if(i4_part_mask & (1 << i)) in hme_pick_eval_merge_candts()
997 S32 i4_part_mask = ENABLE_ALL_PARTS - ENABLE_NxN; in hme_try_merge_high_speed() local
1018 i4_part_mask &= ~ENABLE_AMP; in hme_try_merge_high_speed()
1023 i4_part_mask &= ~ENABLE_AMP; in hme_try_merge_high_speed()
1025 i4_part_mask &= ~ENABLE_SMP; in hme_try_merge_high_speed()
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Dhme_err_compute.h119 PF_RESULT_FXN_T hme_get_result_fxn(S32 i4_grid_mask, S32 i4_part_mask, S32 i4_num_results);
Dhme_defs.h1453 S32 i4_part_mask; member
1918 S32 i4_part_mask; member
1992 S32 i4_part_mask; member
2170 S32 i4_part_mask; member
2385 S32 i4_part_mask; member
Dihevce_me_common_defs.h614 WORD32 i4_part_mask; member
Dhme_err_compute.c447 ASSERT((ps_prms->i4_part_mask & (ps_prms->i4_part_mask - 1)) == 0); in hme_evalsad_grid_npu_MxN()
2063 PF_RESULT_FXN_T hme_get_result_fxn(S32 i4_grid_mask, S32 i4_part_mask, S32 i4_num_results) in hme_get_result_fxn() argument
2066 S32 i4_is_pu = ((i4_part_mask & (i4_part_mask - 1)) != 0); in hme_get_result_fxn()
3607 WORD32 i4_grid_mask, i4_part_mask, i4_num_results, i4_candt, i4_num_nodes; in hme_calc_pt_sad_and_result_explicit() local
3618 i4_part_mask = ps_search_prms->i4_part_mask; in hme_calc_pt_sad_and_result_explicit()
3630 pf_sad_fxn = hme_get_sad_fxn(e_blk_size, i4_grid_mask, i4_part_mask); in hme_calc_pt_sad_and_result_explicit()
/external/libhevc/encoder/arm/
Dihevce_me_neon.c421 assert((ps_prms->i4_part_mask & (ps_prms->i4_part_mask - 1)) == 0); in hme_evalsad_grid_npu_MxN_neon()