Home
last modified time | relevance | path

Searched refs:i9 (Results 1 – 25 of 292) sorted by relevance

12345678910>>...12

/external/llvm-project/polly/lib/External/isl/test_inputs/codegen/cloog/
Dequality2.st1 domain: "{ S1[i0, i1, 1, 2, i0, i5, -999 + i1, i0, -999 + i1, i9, i10] : 2i5 = 2 + i1 and 2i9 = -99…
5 …i9, i10] -> [(i0)]; S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14] -> [(i0)] …
9 - filter: "{ S1[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10] }"
10 - filter: "{ S2[i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14] }"
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dcall.ll517 declare i9 @llvm.fshr.i9(i9, i9, i9)
529 define i9 @fshr_no_shift(i9 %x, i9 %y) {
531 ; CHECK-NEXT: ret i9 [[Y:%.*]]
533 %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 0)
534 ret i9 %z
545 define i9 @fshr_no_shift_modulo_bitwidth(i9 %x, i9 %y) {
547 ; CHECK-NEXT: ret i9 [[Y:%.*]]
549 %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 189)
550 ret i9 %z
625 define i9 @fshr_zero_shift_guard(i9 %x, i9 %y, i9 %sh) {
[all …]
Dshift-knownbits.ll59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
61 ; CHECK-NEXT: ret i9 [[A:%.*]]
63 %and = and i9 %b, 496 ; 0x1f0
64 %shl = shl i9 %a, %and
65 ret i9 %shl
71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) {
73 ; CHECK-NEXT: [[AND:%.*]] = and i9 [[B:%.*]], -8
74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 [[A:%.*]], [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
77 %and = and i9 %b, 504 ; 0x1f8
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dshould-change-type.ll44 define i9 @test4(i9 %x, i9 %y) {
46 ; CHECK-NEXT: [[XZ:%.*]] = zext i9 [[X:%.*]] to i64
47 ; CHECK-NEXT: [[YZ:%.*]] = zext i9 [[Y:%.*]] to i64
49 ; CHECK-NEXT: [[D:%.*]] = trunc i64 [[C]] to i9
50 ; CHECK-NEXT: ret i9 [[D]]
52 %xz = zext i9 %x to i64
53 %yz = zext i9 %y to i64
55 %d = trunc i64 %c to i9
56 ret i9 %d
Dudivrem-change-width.ll95 define i32 @udiv_illegal_type(i9 %a, i9 %b) {
97 ; CHECK-NEXT: [[DIV:%.*]] = udiv i9 %a, %b
98 ; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[DIV]] to i32
101 %za = zext i9 %a to i32
102 %zb = zext i9 %b to i32
148 define i32 @urem_illegal_type(i9 %a, i9 %b) {
150 ; CHECK-NEXT: [[TMP1:%.*]] = urem i9 %a, %b
151 ; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32
154 %za = zext i9 %a to i32
155 %zb = zext i9 %b to i32
[all …]
Dapint-shift.ll91 define i9 @multiuse_lshr_lshr(i9 %x) {
93 ; CHECK-NEXT: [[SH1:%.*]] = lshr i9 [[X:%.*]], 2
94 ; CHECK-NEXT: [[SH2:%.*]] = lshr i9 [[X]], 5
95 ; CHECK-NEXT: [[MUL:%.*]] = mul i9 [[SH1]], [[SH2]]
96 ; CHECK-NEXT: ret i9 [[MUL]]
98 %sh1 = lshr i9 %x, 2
99 %sh2 = lshr i9 %sh1, 3
100 %mul = mul i9 %sh1, %sh2
101 ret i9 %mul
104 define <2 x i9> @multiuse_lshr_lshr_splat(<2 x i9> %x) {
[all …]
Dselect-select.ll62 define <5 x i9> @sel_shuf_commute1(<5 x i9> %x, <5 x i9> %y, <5 x i1> %cmp) {
64 ; CHECK-NEXT: [[SEL:%.*]] = select <5 x i1> [[CMP:%.*]], <5 x i9> [[X:%.*]], <5 x i9> [[Y:%.*]]
65 ; CHECK-NEXT: [[R:%.*]] = shufflevector <5 x i9> [[SEL]], <5 x i9> [[Y]], <5 x i32> <i32 0, i32 …
66 ; CHECK-NEXT: ret <5 x i9> [[R]]
68 %blend = shufflevector <5 x i9> %x, <5 x i9> %y, <5 x i32> <i32 0, i32 6, i32 2, i32 8, i32 9>
69 %r = select <5 x i1> %cmp, <5 x i9> %blend, <5 x i9> %y
70 ret <5 x i9> %r
/external/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dweird-type-accesses.ll14 declare void @use_v2i9(<2 x i9>)
178 ; CHECK: store i9 3
179 ; CHECK: store i9 -5
180 define void @merge_store_2_constants_i9(i9 addrspace(1)* %out) #0 {
181 %out.gep.1 = getelementptr i9, i9 addrspace(1)* %out, i32 1
182 store i9 3, i9 addrspace(1)* %out.gep.1
183 store i9 -5, i9 addrspace(1)* %out
188 ; CHECK: load <2 x i9>
189 ; CHECK: load <2 x i9>
190 define void @merge_load_2_constants_v2i9(<2 x i9> addrspace(1)* %out) #0 {
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
61 ; CHECK-NEXT: ret i9 %a
63 %and = and i9 %b, 496 ; 0x1f0
64 %shl = shl i9 %a, %and
65 ret i9 %shl
71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) {
73 ; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8
74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
77 %and = and i9 %b, 504 ; 0x1f8
[all …]
/external/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dweird-type-accesses.ll16 declare void @use_v2i9(<2 x i9>)
180 ; CHECK: store i9 3
181 ; CHECK: store i9 -5
182 define amdgpu_kernel void @merge_store_2_constants_i9(i9 addrspace(1)* %out) #0 {
183 %out.gep.1 = getelementptr i9, i9 addrspace(1)* %out, i32 1
184 store i9 3, i9 addrspace(1)* %out.gep.1
185 store i9 -5, i9 addrspace(1)* %out
190 ; CHECK: load <2 x i9>
191 ; CHECK: load <2 x i9>
192 define amdgpu_kernel void @merge_load_2_constants_v2i9(<2 x i9> addrspace(1)* %out) #0 {
[all …]
/external/llvm/test/CodeGen/X86/
D2009-07-20-DAGCombineBug.ll14 bb3.i9: ; preds = %bb3.i17
17 bb1.i15: ; preds = %bb3.i9
20 bb2.i16: ; preds = %bb3.i9
24 br i1 false, label %bb3.i9, label %bsR.exit18
/external/llvm-project/llvm/test/CodeGen/X86/
D2009-07-20-DAGCombineBug.ll14 bb3.i9: ; preds = %bb3.i17
17 bb1.i15: ; preds = %bb3.i9
20 bb2.i16: ; preds = %bb3.i9
24 br i1 false, label %bb3.i9, label %bsR.exit18
/external/llvm/test/Analysis/ScalarEvolution/
Dsext-iv-1.ll24 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
47 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
70 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
71 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
93 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
94 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
/external/clang/test/CodeGen/
Darm64-arguments.c298 int i9, s38_no_align s1, s38_no_align s2) { in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
351 int i9, s39_with_align s1, s39_with_align s2) { in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
406 int i9, s40_no_align s1, s40_no_align s2) { in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
461 int i9, s41_with_align s1, s41_with_align s2) { in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
518 int i9, s42_no_align s1, s42_no_align s2) { in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/llvm-project/clang/test/CodeGen/
Darm64-arguments.c298 int i9, s38_no_align s1, s38_no_align s2) { in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
351 int i9, s39_with_align s1, s39_with_align s2) { in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
406 int i9, s40_no_align s1, s40_no_align s2) { in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
461 int i9, s41_with_align s1, s41_with_align s2) { in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
518 int i9, s42_no_align s1, s42_no_align s2) { in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dsext-iv-1.ll24 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
47 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
70 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
71 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
93 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1]
94 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
/external/llvm/test/tools/llvm-nm/X86/
Dradix.s74 .type i9,@object # @i9
75 .globl i9 symbol
77 i9: label
79 .size i9, 4
/external/llvm-project/llvm/test/tools/llvm-nm/X86/
Dradix.s74 .type i9,@object # @i9
75 .globl i9 symbol
77 i9: label
79 .size i9, 4
/external/llvm-project/mlir/test/Dialect/Affine/
Dslicing-utils.mlir26 // FWD-NEXT: %[[v9:.*]] {{.*}} -> i9
39 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
47 // FWD-NEXT: %[[v9:.*]] {{.*}} -> i9
60 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
67 // FWD-NEXT: %[[v9:.*]] {{.*}} -> i9
80 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
87 // FWD-NEXT: %[[v9:.*]] {{.*}} -> i9
100 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
107 // FWD-NEXT: %[[v9:.*]] {{.*}} -> i9
122 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
[all …]
/external/llvm-project/openmp/runtime/test/misc_bugs/
Dmany-microtask-args.c16 int i9 = 9; in main() local
26 …#pragma omp parallel for firstprivate(i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14,… in main()
28 r += i + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + i10 + i11 + i12 + i13 + i14 + i15 + i16; in main()
/external/XNNPACK/src/f32-dwconv/gen/
Dup2x25-scalar.c77 const float* i9 = input[9]; in xnn_f32_dwconv_ukernel_up2x25__scalar() local
78 assert(i9 != NULL); in xnn_f32_dwconv_ukernel_up2x25__scalar()
79 if XNN_UNPREDICTABLE(i9 != zero) { in xnn_f32_dwconv_ukernel_up2x25__scalar()
80 i9 = (const float*) ((uintptr_t) i9 + input_offset); in xnn_f32_dwconv_ukernel_up2x25__scalar()
247 const float vi9x0 = i9[0]; in xnn_f32_dwconv_ukernel_up2x25__scalar()
248 const float vi9x1 = i9[1]; in xnn_f32_dwconv_ukernel_up2x25__scalar()
249 i9 += 2; in xnn_f32_dwconv_ukernel_up2x25__scalar()
428 const float vi9 = *i9++; in xnn_f32_dwconv_ukernel_up2x25__scalar()
Dup2x25-wasm-acc2.c77 const float* i9 = input[9]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2() local
78 assert(i9 != NULL); in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
79 if XNN_UNPREDICTABLE(i9 != zero) { in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
80 i9 = (const float*) ((uintptr_t) i9 + input_offset); in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
247 const float vi9x0 = i9[0]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
248 const float vi9x1 = i9[1]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
249 i9 += 2; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
431 const float vi9 = *i9++; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
Dup2x25-scalar-acc2.c77 const float* i9 = input[9]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2() local
78 assert(i9 != NULL); in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
79 if XNN_UNPREDICTABLE(i9 != zero) { in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
80 i9 = (const float*) ((uintptr_t) i9 + input_offset); in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
247 const float vi9x0 = i9[0]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
248 const float vi9x1 = i9[1]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
249 i9 += 2; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
431 const float vi9 = *i9++; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
Dup2x25-wasm.c77 const float* i9 = input[9]; in xnn_f32_dwconv_ukernel_up2x25__wasm() local
78 assert(i9 != NULL); in xnn_f32_dwconv_ukernel_up2x25__wasm()
79 if XNN_UNPREDICTABLE(i9 != zero) { in xnn_f32_dwconv_ukernel_up2x25__wasm()
80 i9 = (const float*) ((uintptr_t) i9 + input_offset); in xnn_f32_dwconv_ukernel_up2x25__wasm()
247 const float vi9x0 = i9[0]; in xnn_f32_dwconv_ukernel_up2x25__wasm()
248 const float vi9x1 = i9[1]; in xnn_f32_dwconv_ukernel_up2x25__wasm()
249 i9 += 2; in xnn_f32_dwconv_ukernel_up2x25__wasm()
428 const float vi9 = *i9++; in xnn_f32_dwconv_ukernel_up2x25__wasm()
Dup1x25-minmax-wasm.c79 const float* i9 = input[9]; in xnn_f32_dwconv_minmax_ukernel_up1x25__wasm() local
80 assert(i9 != NULL); in xnn_f32_dwconv_minmax_ukernel_up1x25__wasm()
81 if XNN_UNPREDICTABLE(i9 != zero) { in xnn_f32_dwconv_minmax_ukernel_up1x25__wasm()
82 i9 = (const float*) ((uintptr_t) i9 + input_offset); in xnn_f32_dwconv_minmax_ukernel_up1x25__wasm()
202 const float vi9 = *i9++; in xnn_f32_dwconv_minmax_ukernel_up1x25__wasm()

12345678910>>...12