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Searched refs:ilvl (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/CodeGen/Mips/msa/
D3r-i.ll103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1)
108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind
113 ; CHECK: ilvl.b
125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1)
130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind
135 ; CHECK: ilvl.h
147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1)
152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind
157 ; CHECK: ilvl.w
169 %2 = tail call <2 x i64> @llvm.mips.ilvl.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dshuffle.ll891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
936 ; ilvl.d and ilvod.d are equivalent for v2i64
952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
994 ; ilvl.d and splati.d are equivalent for v2i64
1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3r-i.ll103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1)
108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind
113 ; CHECK: ilvl.b
125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1)
130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind
135 ; CHECK: ilvl.h
147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1)
152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind
157 ; CHECK: ilvl.w
169 %2 = tail call <2 x i64> @llvm.mips.ilvl.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dshuffle.ll891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]]
906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]]
921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]]
936 ; ilvl.d and ilvod.d are equivalent for v2i64
952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]]
994 ; ilvl.d and splati.d are equivalent for v2i64
1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]]
1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]]
[all …]
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs128 0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21
129 0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17
130 0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0
131 0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24
/external/llvm-project/llvm/lib/Target/Mips/
DMSA.txt35 ilvl.d, pckev.d:
36 It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
DMipsMSAInstrInfo.td2249 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2250 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2251 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2252 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
/external/llvm/lib/Target/Mips/
DMSA.txt35 ilvl.d, pckev.d:
36 It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
DMipsMSAInstrInfo.td2230 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2231 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2232 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2233 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMSA.txt35 ilvl.d, pckev.d:
36 It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
DMipsMSAInstrInfo.td2249 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2250 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2251 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2252 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54]
130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4]
131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94]
132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4]
372 ilvl.b $w29, $w3, $w21
373 ilvl.h $w27, $w10, $w17
374 ilvl.w $w6, $w1, $w0
375 ilvl.d $w3, $w16, $w24
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_3r.s129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54]
130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4]
131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94]
132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4]
372 ilvl.b $w29, $w3, $w21
373 ilvl.h $w27, $w10, $w17
374 ilvl.w $w6, $w1, $w0
375 ilvl.d $w3, $w16, $w24
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt129 0x7a 0x15 0x1f 0x54 # CHECK: ilvl.b $w29, $w3, $w21
130 0x7a 0x31 0x56 0xd4 # CHECK: ilvl.h $w27, $w10, $w17
131 0x7a 0x40 0x09 0x94 # CHECK: ilvl.w $w6, $w1, $w0
132 0x7a 0x78 0x80 0xd4 # CHECK: ilvl.d $w3, $w16, $w24
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt129 0x7a 0x15 0x1f 0x54 # CHECK: ilvl.b $w29, $w3, $w21
130 0x7a 0x31 0x56 0xd4 # CHECK: ilvl.h $w27, $w10, $w17
131 0x7a 0x40 0x09 0x94 # CHECK: ilvl.w $w6, $w1, $w0
132 0x7a 0x78 0x80 0xd4 # CHECK: ilvl.d $w3, $w16, $w24
/external/tcpdump/
Dprint-forces.c747 int ilvl = EXTRACT_32BITS(&ilv->length); in sdatailv_print() local
749 EXTRACT_32BITS(&ilv->type), ilvl)); in sdatailv_print()
750 hex_print_with_offset(ndo, "\t\t[", tdp, ilvl-ILV_HDRL, 0); in sdatailv_print()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5022 "sub_u.w\007hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl."
5023 "b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilv"
6721 …{ 5133 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
6722 …{ 5140 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
6723 …{ 5147 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
6724 …{ 5154 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
9987 { 5133 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9988 { 5140 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9989 { 5147 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9990 { 5154 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen2552 mips_ilvl_b, // llvm.mips.ilvl.b
2553 mips_ilvl_d, // llvm.mips.ilvl.d
2554 mips_ilvl_h, // llvm.mips.ilvl.h
2555 mips_ilvl_w, // llvm.mips.ilvl.w
8610 "llvm.mips.ilvl.b",
8611 "llvm.mips.ilvl.d",
8612 "llvm.mips.ilvl.h",
8613 "llvm.mips.ilvl.w",
16550 1, // llvm.mips.ilvl.b
16551 1, // llvm.mips.ilvl.d
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen2552 mips_ilvl_b, // llvm.mips.ilvl.b
2553 mips_ilvl_d, // llvm.mips.ilvl.d
2554 mips_ilvl_h, // llvm.mips.ilvl.h
2555 mips_ilvl_w, // llvm.mips.ilvl.w
8610 "llvm.mips.ilvl.b",
8611 "llvm.mips.ilvl.d",
8612 "llvm.mips.ilvl.h",
8613 "llvm.mips.ilvl.w",
16550 1, // llvm.mips.ilvl.b
16551 1, // llvm.mips.ilvl.d
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen2552 mips_ilvl_b, // llvm.mips.ilvl.b
2553 mips_ilvl_d, // llvm.mips.ilvl.d
2554 mips_ilvl_h, // llvm.mips.ilvl.h
2555 mips_ilvl_w, // llvm.mips.ilvl.w
8610 "llvm.mips.ilvl.b",
8611 "llvm.mips.ilvl.d",
8612 "llvm.mips.ilvl.h",
8613 "llvm.mips.ilvl.w",
16550 1, // llvm.mips.ilvl.b
16551 1, // llvm.mips.ilvl.d
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen2552 mips_ilvl_b, // llvm.mips.ilvl.b
2553 mips_ilvl_d, // llvm.mips.ilvl.d
2554 mips_ilvl_h, // llvm.mips.ilvl.h
2555 mips_ilvl_w, // llvm.mips.ilvl.w
8610 "llvm.mips.ilvl.b",
8611 "llvm.mips.ilvl.d",
8612 "llvm.mips.ilvl.h",
8613 "llvm.mips.ilvl.w",
16550 1, // llvm.mips.ilvl.b
16551 1, // llvm.mips.ilvl.d
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen2546 mips_ilvl_b, // llvm.mips.ilvl.b
2547 mips_ilvl_d, // llvm.mips.ilvl.d
2548 mips_ilvl_h, // llvm.mips.ilvl.h
2549 mips_ilvl_w, // llvm.mips.ilvl.w
8570 "llvm.mips.ilvl.b",
8571 "llvm.mips.ilvl.d",
8572 "llvm.mips.ilvl.h",
8573 "llvm.mips.ilvl.w",
16455 1, // llvm.mips.ilvl.b
16456 1, // llvm.mips.ilvl.d
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc4033 "llvm.mips.ilvl.b",
4034 "llvm.mips.ilvl.d",
4035 "llvm.mips.ilvl.h",
4036 "llvm.mips.ilvl.w",
14166 1, // llvm.mips.ilvl.b
14167 1, // llvm.mips.ilvl.d
14168 1, // llvm.mips.ilvl.h
14169 1, // llvm.mips.ilvl.w