Home
last modified time | relevance | path

Searched refs:imm16 (Results 1 – 25 of 92) sorted by relevance

1234

/external/vixl/test/aarch32/config/
Dcond-rd-operand-imm16-t32.json28 // MNEMONIC{<c>}.W <Rd>, #<imm16>
32 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
33 "Movt", // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
34 "Movw" // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3
84 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
85 "Movt" // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrFormats.td75 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
76 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
79 bits<16> imm16;
82 let Inst{15 - 0} = imm16;
88 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
89 !strconcat(op, "\t$rz, $imm16"),
90 [(set GPR:$rz, ImmType:$imm16)]> {
92 bits<16> imm16;
95 let Inst{15 - 0} = imm16;
105 (outs GPR:$rz), (ins operand:$imm16),
[all …]
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td436 bits<16> imm16;
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
445 let Inst{4-0} = imm16{4-0};
487 bits<16> imm16;
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
498 let Inst{4-0} = imm16{4-0};
512 bits<16> imm16;
518 let Inst{26-21} = imm16{10-5};
[all …]
DMipsInstrFormats.td177 bits<16> imm16;
183 let Inst{15-0} = imm16;
192 bits<16> imm16;
198 let Inst{15-0} = imm16;
236 bits<16> imm16;
243 let Inst{15-0} = imm16;
264 bits<16> imm16;
271 let Inst{15-0} = imm16;
347 bits<16> imm16;
354 let Inst{15-0} = imm16;
[all …]
DMips16InstrInfo.td55 FI16<op, (outs), (ins brtarget:$imm16),
56 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
152 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
153 !strconcat(asmstr, "\t$imm16"),[], itin>;
1356 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1394 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1395 (I CPU16Regs:$rx, imm_type:$imm16)>;
1431 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1432 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td435 bits<16> imm16;
440 let Inst{26-21} = imm16{10-5};
441 let Inst{20-16} = imm16{15-11};
444 let Inst{4-0} = imm16{4-0};
486 bits<16> imm16;
492 let Inst{26-21} = imm16{10-5};
493 let Inst{20-16} = imm16{15-11};
497 let Inst{4-0} = imm16{4-0};
511 bits<16> imm16;
517 let Inst{26-21} = imm16{10-5};
[all …]
DMipsInstrFormats.td180 bits<16> imm16;
186 let Inst{15-0} = imm16;
195 bits<16> imm16;
201 let Inst{15-0} = imm16;
239 bits<16> imm16;
246 let Inst{15-0} = imm16;
267 bits<16> imm16;
274 let Inst{15-0} = imm16;
350 bits<16> imm16;
357 let Inst{15-0} = imm16;
[all …]
DMips16InstrInfo.td54 FI16<op, (outs), (ins brtarget:$imm16),
55 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
151 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
152 !strconcat(asmstr, "\t$imm16"),[], itin>;
1359 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1397 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1398 (I CPU16Regs:$rx, imm_type:$imm16)>;
1426 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1427 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1445 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td435 bits<16> imm16;
440 let Inst{26-21} = imm16{10-5};
441 let Inst{20-16} = imm16{15-11};
444 let Inst{4-0} = imm16{4-0};
486 bits<16> imm16;
492 let Inst{26-21} = imm16{10-5};
493 let Inst{20-16} = imm16{15-11};
497 let Inst{4-0} = imm16{4-0};
511 bits<16> imm16;
517 let Inst{26-21} = imm16{10-5};
[all …]
DMips16InstrInfo.td54 FI16<op, (outs), (ins brtarget:$imm16),
55 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
151 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
152 !strconcat(asmstr, "\t$imm16"),[], itin>;
1359 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1397 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1398 (I CPU16Regs:$rx, imm_type:$imm16)>;
1426 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1427 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1445 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
[all …]
DMipsInstrFormats.td206 bits<16> imm16;
213 let Inst{15-0} = imm16;
234 bits<16> imm16;
241 let Inst{15-0} = imm16;
317 bits<16> imm16;
324 let Inst{15-0} = imm16;
382 bits<16> imm16;
389 let Inst{15-0} = imm16;
503 bits<16> imm16;
510 let Inst{15-0} = imm16;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
285 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
411 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
412 "mov\t$imm16, $Rd",
413 [(set GPR:$Rd, i32hi16:$imm16)]>;
415 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
[all …]
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
408 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
409 "mov\t$imm16, $Rd",
410 [(set GPR:$Rd, i32hi16:$imm16)]>;
412 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
408 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
409 "mov\t$imm16, $Rd",
410 [(set GPR:$Rd, i32hi16:$imm16)]>;
412 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td351 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
352 !strconcat(OpcStr, " $rs1, $imm16"), []>;
353 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
355 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
357 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
363 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td350 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
351 !strconcat(OpcStr, " $rs1, $imm16"), []>;
352 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
354 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
356 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
362 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
[all …]
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td350 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
351 !strconcat(OpcStr, " $rs1, $imm16"), []>;
352 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
353 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
354 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
355 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
356 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
357 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
361 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
362 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
[all …]
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx9_uimm16.rst10 imm16 title
Dgfx8_uimm16.rst10 imm16 title
Dgfx8_simm16.rst10 imm16 title
Dgfx7_simm16.rst10 imm16 title
Dgfx9_simm16.rst10 imm16 title
Dgfx7_uimm16.rst10 imm16 title
Dgfx10_simm16.rst10 imm16 title
Dgfx10_uimm16.rst10 imm16 title

1234