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Searched refs:imm19 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.td797 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
798 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
801 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
802 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
805 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
806 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
809 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
810 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
856 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
858 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
[all …]
DSparcInstrFormats.td74 bits<19> imm19;
83 let Inst{18-0} = imm19;
DSparcInstr64Bit.td311 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrInfo.td797 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
798 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
801 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
802 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
805 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
806 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
809 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
810 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
856 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
858 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
[all …]
DSparcInstrFormats.td74 bits<19> imm19;
83 let Inst{18-0} = imm19;
DSparcInstr64Bit.td311 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td792 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
793 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
796 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
797 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
800 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
801 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
804 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
805 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
851 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
853 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
[all …]
DSparcInstrFormats.td75 bits<19> imm19;
84 let Inst{18-0} = imm19;
DSparcInstr64Bit.td312 defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h544 void b(int64_t imm19, Condition cond);
556 void cbz(const Register& rt, int64_t imm19);
562 void cbnz(const Register& rt, int64_t imm19);
1291 void ldr(const CPURegister& rt, int64_t imm19);
1294 void ldrsw(const Register& xt, int64_t imm19);
2065 void prfm(PrefetchOperation op, int64_t imm19);
2081 void prfm(int op, int64_t imm19);
5968 static Instr ImmCondBranch(int64_t imm19) { in ImmCondBranch() argument
5969 VIXL_ASSERT(IsInt19(imm19)); in ImmCondBranch()
5970 return TruncateToUint19(imm19) << ImmCondBranch_offset; in ImmCondBranch()
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Dassembler-aarch64.cc122 ptrdiff_t imm19 = ldr->GetImmLLiteral(); in place() local
123 VIXL_ASSERT(imm19 <= 0); in place()
124 done = (imm19 == 0); in place()
125 offset += imm19 * kLiteralEntrySize; in place()
261 void Assembler::b(int64_t imm19, Condition cond) { in b() argument
262 Emit(B_cond | ImmCondBranch(imm19) | cond); in b()
290 void Assembler::cbz(const Register& rt, int64_t imm19) { in cbz() argument
291 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); in cbz()
302 void Assembler::cbnz(const Register& rt, int64_t imm19) { in cbnz() argument
303 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); in cbnz()
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/external/llvm-project/lldb/source/Plugins/Instruction/ARM64/
DEmulateInstructionARM64.cpp1092 bits(64) offset = SignExtend(imm19:'00', 64); in EmulateBcond()
1123 bits(64) offset = SignExtend(imm19:'00', 64); in EmulateCBZ()
/external/skia/src/core/
DSkVM.cpp2235 const int imm19 = this->disp19(l); in b() local
2236 this->op(0b0101010'0'00000000000000, (X)0, (V)cond, (imm19 & 19_mask) << 5); in b()
2239 const int imm19 = this->disp19(l); in cbz() local
2240 this->op(0b1'011010'0'00000000000000, (X)0, t, (imm19 & 19_mask) << 5); in cbz()
2243 const int imm19 = this->disp19(l); in cbnz() local
2244 this->op(0b1'011010'1'00000000000000, (X)0, t, (imm19 & 19_mask) << 5); in cbnz()
2307 const int imm19 = this->disp19(l); in ldrq() local
2308 this->op(0b10'011'1'00'00000000000000, (V)0, dst, (imm19 & 19_mask) << 5); in ldrq()
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md247 void b(int64_t imm19, Condition cond)
552 void cbnz(const Register& rt, int64_t imm19)
566 void cbz(const Register& rt, int64_t imm19)
1282 Load integer or FP register from pc + imm19 << 2.
1284 void ldr(const CPURegister& rt, int64_t imm19)
1355 Load word with sign extension from pc + imm19 << 2.
1357 void ldrsw(const Register& xt, int64_t imm19)
2180 Prefetch from pc + imm19 << 2.
2182 void prfm(PrefetchOperation op, int64_t imm19)