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Searched refs:imm2 (Results 1 – 25 of 37) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dconstants-i64.ll199 define i64 @imm2() #0 {
200 ; CHECK-LABEL: imm2:
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrFormats.td148 (ins GPR:$rx, operand:$imm2),
149 !strconcat(op, "\t$rx, $imm2"), pattern> {
151 bits<2> imm2;
155 let Inst{1 - 0} = imm2;
/external/llvm/lib/Target/Mips/
DMips32r6InstrFormats.td493 bits<2> imm2;
502 let Inst{7-6} = imm2;
DMicroMips32r6InstrFormats.td412 bits<2> imm2;
420 let Inst{10-9} = imm2;
DMips32r6InstrInfo.td671 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
672 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
DMicroMips32r6InstrInfo.td543 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
544 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
/external/llvm-project/llvm/lib/Target/Mips/
DMips32r6InstrFormats.td508 bits<2> imm2;
517 let Inst{7-6} = imm2;
DMicroMips32r6InstrFormats.td362 bits<2> imm2;
370 let Inst{10-9} = imm2;
DMips32r6InstrInfo.td749 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
750 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips32r6InstrFormats.td508 bits<2> imm2;
517 let Inst{7-6} = imm2;
DMicroMips32r6InstrFormats.td362 bits<2> imm2;
370 let Inst{10-9} = imm2;
DMips32r6InstrInfo.td749 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
750 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
/external/pcre/dist2/src/sljit/
DsljitNativeARM_32.c1304 sljit_uw imm2; in generate_int() local
1347 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8); in generate_int()
1370 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1400 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1406 FAIL_IF(push_inst(compiler, (positive ? ORR : BIC) | RD(reg) | RN(reg) | imm2)); in generate_int()
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_peephole.cpp788 ImmediateValue &imm2) in expr() argument
790 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
904 const int s, ImmediateValue& imm2) in tryCollapseChainedMULs() argument
910 float f = imm2.reg.data.f32 * exp2f(mul2->postFactor); in tryCollapseChainedMULs()
968 ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2) in opnd3() argument
973 if (imm2.isInteger(0)) { in opnd3()
981 if (imm2.isInteger(0)) { in opnd3()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc210 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2781 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) { in TestOpImmOpImmNEON() local
2790 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2817 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2822 unsigned input_index_imm2 = imm2; in TestOpImmOpImmNEON()
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td265 // t2addrmode_so_reg := reg + (reg << imm2)
602 let Inst{7-6} = 0b00; // imm2
686 let Inst{7-6} = 0b00; // imm2
807 let Inst{7-6} = 0b00; // imm2
849 let Inst{7-6} = 0b00; // imm2
947 let Inst{7-6} = 0b00; // imm2
1670 let Inst{5-4} = addr{1-0}; // imm2
2261 let Inst{7-6} = 0b00; // imm2 = '00'
2284 let Inst{7-6} = 0b00; // imm2 = '00'
2489 let Inst{7-6} = 0b00; // imm2
[all …]
/external/vixl/src/aarch64/
Dassembler-aarch64.h6213 static Instr ImmBarrierDomain(int imm2) { in ImmBarrierDomain() argument
6214 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierDomain()
6215 return imm2 << ImmBarrierDomain_offset; in ImmBarrierDomain()
6218 static Instr ImmBarrierType(int imm2) { in ImmBarrierType() argument
6219 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierType()
6220 return imm2 << ImmBarrierType_offset; in ImmBarrierType()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1571 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1572 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1795 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1796 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1583 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1584 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td336 // t2addrmode_so_reg := reg + (reg << imm2)
756 let Inst{7-6} = 0b00; // imm2
842 let Inst{7-6} = 0b00; // imm2
999 let Inst{7-6} = 0b00; // imm2
1041 let Inst{7-6} = 0b00; // imm2
1140 let Inst{7-6} = 0b00; // imm2
1864 let Inst{5-4} = addr{1-0}; // imm2
2796 let Inst{7-6} = 0b00; // imm2
3317 let Inst{7-6} = 0b00; // imm2
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td337 // t2addrmode_so_reg := reg + (reg << imm2)
757 let Inst{7-6} = 0b00; // imm2
843 let Inst{7-6} = 0b00; // imm2
1000 let Inst{7-6} = 0b00; // imm2
1042 let Inst{7-6} = 0b00; // imm2
1141 let Inst{7-6} = 0b00; // imm2
1867 let Inst{5-4} = addr{1-0}; // imm2
2865 let Inst{7-6} = 0b00; // imm2
3386 let Inst{7-6} = 0b00; // imm2
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
/external/llvm/lib/Target/X86/
DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
/external/llvm-project/llvm/lib/Target/X86/
DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert

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