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Searched refs:imm26 (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td414 bits<26> imm26;
421 let Inst{25-21} = imm26{20-16};
422 let Inst{20-16} = imm26{25-21};
423 let Inst{15-0} = imm26{15-0};
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td413 bits<26> imm26;
420 let Inst{25-21} = imm26{20-16};
421 let Inst{20-16} = imm26{25-21};
422 let Inst{15-0} = imm26{15-0};
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td413 bits<26> imm26;
420 let Inst{25-21} = imm26{20-16};
421 let Inst{20-16} = imm26{25-21};
422 let Inst{15-0} = imm26{15-0};
/external/vixl/src/aarch64/
Dassembler-aarch64.h541 void b(int64_t imm26);
550 void bl(int64_t imm26);
5963 static Instr ImmUncondBranch(int64_t imm26) { in ImmUncondBranch() argument
5964 VIXL_ASSERT(IsInt26(imm26)); in ImmUncondBranch()
5965 return TruncateToUint26(imm26) << ImmUncondBranch_offset; in ImmUncondBranch()
Dassembler-aarch64.cc258 void Assembler::b(int64_t imm26) { Emit(B | ImmUncondBranch(imm26)); } in b() argument
280 void Assembler::bl(int64_t imm26) { Emit(BL | ImmUncondBranch(imm26)); } in bl() argument
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md261 void b(int64_t imm26)
326 void bl(int64_t imm26)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc4249 // op: imm26