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Searched refs:imm3 (Results 1 – 25 of 38) sorted by relevance

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/external/mesa3d/src/compiler/glsl/
Dlower_blend_equation_advanced.cpp37 #define imm3(x) new(mem_ctx) ir_constant((float) (x), 3) macro
61 ir_rvalue *rule_1 = mul(imm3(2), mul(src, dst)); in blend_overlay()
63 sub(imm3(1), mul(imm3(2), mul(sub(imm3(1), src), sub(imm3(1), dst)))); in blend_overlay()
64 return csel(lequal(dst, imm3(0.5f)), rule_1, rule_2); in blend_overlay()
91 return csel(lequal(dst, imm3(0)), imm3(0), in blend_colordodge()
92 csel(gequal(src, imm3(1)), imm3(1), in blend_colordodge()
93 min2(imm3(1), div(dst, sub(imm3(1), src))))); in blend_colordodge()
106 return csel(gequal(dst, imm3(1)), imm3(1), in blend_colorburn()
107 csel(lequal(src, imm3(0)), imm3(0), in blend_colorburn()
108 sub(imm3(1), min2(imm3(1), div(sub(imm3(1), dst), src))))); in blend_colorburn()
[all …]
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json29 // MNEMONIC{<c>}.N <Rd>, <Rn>, #<imm3>
34 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
37 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
42 "Sub", // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
45 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
174 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
175 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
191 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
192 "Sub" // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DARMUtils.h307 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbExpandImm_C() local
309 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C()
350 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbImm12() local
352 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12()
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx8_perm_smem.rst10 imm3 title
Dgfx10_perm_smem.rst10 imm3 title
Dgfx9_perm_smem.rst10 imm3 title
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td955 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
957 "add", "\t$Rd, $Rm, $imm3",
958 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
960 bits<3> imm3;
961 let Inst{8-6} = imm3;
993 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
996 imm0_7:$imm3))]>,
1298 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1300 "sub", "\t$Rd, $Rm, $imm3",
1301 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
[all …]
DARMInstrThumb2.td755 let Inst{14-12} = 0b000; // imm3
841 let Inst{14-12} = 0b000; // imm3
998 let Inst{14-12} = 0b000; // imm3
1040 let Inst{14-12} = 0b000; // imm3
1138 let Inst{14-12} = 0b000; // imm3
2795 let Inst{14-12} = 0b000; // imm3
3315 let Inst{14-12} = 0b000; // imm3
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td967 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
969 "add", "\t$Rd, $Rm, $imm3",
970 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
972 bits<3> imm3;
973 let Inst{8-6} = imm3;
1005 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1008 imm0_7:$imm3))]>,
1310 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1312 "sub", "\t$Rd, $Rm, $imm3",
1313 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
[all …]
DARMInstrThumb2.td756 let Inst{14-12} = 0b000; // imm3
842 let Inst{14-12} = 0b000; // imm3
999 let Inst{14-12} = 0b000; // imm3
1041 let Inst{14-12} = 0b000; // imm3
1139 let Inst{14-12} = 0b000; // imm3
2864 let Inst{14-12} = 0b000; // imm3
3384 let Inst{14-12} = 0b000; // imm3
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dconstants-i64.ll210 define i64 @imm3() #0 {
211 ; CHECK-LABEL: imm3:
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td916 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
918 "add", "\t$Rd, $Rm, $imm3",
919 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
921 bits<3> imm3;
922 let Inst{8-6} = imm3;
1203 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1205 "sub", "\t$Rd, $Rm, $imm3",
1206 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1208 bits<3> imm3;
1209 let Inst{8-6} = imm3;
DARMInstrThumb2.td601 let Inst{14-12} = 0b000; // imm3
685 let Inst{14-12} = 0b000; // imm3
806 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
945 let Inst{14-12} = 0b000; // imm3
2260 let Inst{14-12} = 0b000; // imm3 = '000'
2283 let Inst{14-12} = 0b000; // imm3 = '000'
2488 let Inst{14-12} = 0b000; // imm3
3106 let Inst{14-12} = 0b000; // imm3
/external/llvm-project/lld/lib/ReaderWriter/MachO/
DArchHandler_arm.cpp482 uint32_t imm3 = ((instruction & 0x70000000) >> 28); in getWordFromThumbMov() local
484 return (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in getWordFromThumbMov()
498 uint32_t imm3 = (word & 0x0700) >> 8; in setWordFromThumbMov() local
500 return (instr & 0x8F00FBF0) | imm4 | (i << 10) | (imm3 << 28) | (imm8 << 16); in setWordFromThumbMov()
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1913 int imm3) { in Ftmad() argument
1920 ftmad(zd, zd, scratch, imm3); in Ftmad()
1923 ftmad(zd, zd, zm, imm3); in Ftmad()
Dassembler-aarch64.h4458 int imm3);
6203 static Instr ImmSysOp1(int imm3) { in ImmSysOp1() argument
6204 VIXL_ASSERT(IsUint3(imm3)); in ImmSysOp1()
6205 return imm3 << SysOp1_offset; in ImmSysOp1()
6208 static Instr ImmSysOp2(int imm3) { in ImmSysOp2() argument
6209 VIXL_ASSERT(IsUint3(imm3)); in ImmSysOp2()
6210 return imm3 << SysOp2_offset; in ImmSysOp2()
Dassembler-sve-aarch64.cc949 int imm3) { in ftmad() argument
961 ImmUnsignedField<18, 16>(imm3)); in ftmad()
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td1453 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3),
1454 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1459 bits<3> imm3;
1463 let Inst{18-16} = imm3;
2901 let Inst{18-16} = imm{2-0}; // imm3
2937 let Inst{18-16} = imm{2-0}; // imm3
2986 let Inst{18-16} = imm{2-0}; // imm3
3096 let Inst{18-16} = imm{2-0}; // imm3
3134 let Inst{18-16} = imm{2-0}; // imm3
3635 let Inst{18-16} = imm{2-0}; // imm3
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DSVEInstrFormats.td1645 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3),
1646 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1651 bits<3> imm3;
1655 let Inst{18-16} = imm3;
3305 let Inst{18-16} = imm{2-0}; // imm3
3345 let Inst{18-16} = imm{2-0}; // imm3
3406 let Inst{18-16} = imm{2-0}; // imm3
3540 let Inst{18-16} = imm{2-0}; // imm3
3578 let Inst{18-16} = imm{2-0}; // imm3
4093 let Inst{18-16} = imm{2-0}; // imm3
[all …]
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp1410 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm() local
1413 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
1895 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm() local
1897 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDSPImm()
3087 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb() local
3089 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDImmThumb()
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc6421 { /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */
6622 { /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc6421 { /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */
6622 { /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */

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