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Searched refs:imm5 (Results 1 – 25 of 44) sorted by relevance

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/external/llvm-project/lldb/source/Plugins/Process/Utility/
DARMUtils.h24 static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5, in DecodeImmShift() argument
31 return imm5; in DecodeImmShift()
34 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
37 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
39 if (imm5 == 0) { in DecodeImmShift()
44 return imm5; in DecodeImmShift()
68 const uint32_t imm5) { in DecodeImmShift() argument
70 return DecodeImmShift(shift_t, imm5, dont_care); in DecodeImmShift()
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrInfo.td69 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
70 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
72 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
73 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
75 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
76 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
DCSKYInstrFormats.td254 (ins GPR:$false, GPR:$rx, ImmType:$imm5),
255 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
258 bits<5> imm5;
263 let Inst{4 - 0} = imm5;
273 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
274 bits<5> imm5;
277 let Inst{25 - 21} = imm5;
287 bits<5> imm5>
289 op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
296 let Inst{4 - 0} = imm5{4 - 0}; // imm5
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td214 // t_addrmode_is4 := reg + imm5 * 4
226 // t_addrmode_is2 := reg + imm5 * 2
238 // t_addrmode_is1 := reg + imm5
658 // Loads: reg/reg and reg/imm5
668 def i : // reg/imm5
680 // Stores: reg/reg and reg/imm5
686 def i : // reg/imm5
962 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
964 "asr", "\t$Rd, $Rm, $imm5",
965 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
/external/llvm-project/lld/ELF/Arch/
DRISCV.cpp280 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
281 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; in relocate()
298 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
299 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td235 // t_addrmode_is4 := reg + imm5 * 4
247 // t_addrmode_is2 := reg + imm5 * 2
259 // t_addrmode_is1 := reg + imm5
695 // Loads: reg/reg and reg/imm5
705 def i : // reg/imm5
717 // Stores: reg/reg and reg/imm5
723 def i : // reg/imm5
1057 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1059 "asr", "\t$Rd, $Rm, $imm5",
1060 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td239 // t_addrmode_is4 := reg + imm5 * 4
251 // t_addrmode_is2 := reg + imm5 * 2
263 // t_addrmode_is1 := reg + imm5
707 // Loads: reg/reg and reg/imm5
717 def i : // reg/imm5
729 // Stores: reg/reg and reg/imm5
735 def i : // reg/imm5
1069 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1071 "asr", "\t$Rd, $Rm, $imm5",
1072 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dunpredictable-MVN-arm.txt8 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc2208 void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) { in index() argument
2217 Emit(INDEX_z_ri | SVESize(zd) | Rd(zd) | Rn(rn) | ImmField<20, 16>(imm5)); in index()
2220 void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) { in index() argument
2229 Emit(INDEX_z_ir | SVESize(zd) | Rd(zd) | ImmField<9, 5>(imm5) | Rm(rm)); in index()
2795 int imm5) { in cmpeq() argument
2804 CompareVectors(pd, pg, zn, imm5, CMPEQ_p_p_zi); in cmpeq()
2810 int imm5) { in cmpge() argument
2819 CompareVectors(pd, pg, zn, imm5, CMPGE_p_p_zi); in cmpge()
2825 int imm5) { in cmpgt() argument
2834 CompareVectors(pd, pg, zn, imm5, CMPGT_p_p_zi); in cmpgt()
[all …]
Dmacro-assembler-aarch64.h3741 int imm5; in Cmpeq() local
3742 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpeq()
3744 cmpeq(pd, pg, zn, imm5); in Cmpeq()
3762 int imm5; in Cmpge() local
3763 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpge()
3765 cmpge(pd, pg, zn, imm5); in Cmpge()
3783 int imm5; in Cmpgt() local
3784 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpgt()
3786 cmpgt(pd, pg, zn, imm5); in Cmpgt()
3843 int imm5; in Cmple() local
[all …]
Dassembler-aarch64.h3810 int imm5);
3822 int imm5);
3834 int imm5);
3870 int imm5);
3906 int imm5);
3918 int imm5);
4501 void index(const ZRegister& zd, const Register& rn, int imm5);
4505 void index(const ZRegister& zd, int imm5, const Register& rm);
4748 int imm5);
4760 int imm5);
[all …]
Dsimulator-aarch64.cc5883 int imm5 = instr->GetImmNEON5(); in VisitNEONCopy() local
5884 int tz = CountTrailingZeros(imm5, 32); in VisitNEONCopy()
5885 int reg_index = imm5 >> (tz + 1); in VisitNEONCopy()
6944 int imm5 = instr->GetImmNEON5(); in VisitNEONScalarCopy() local
6945 int tz = CountTrailingZeros(imm5, 32); in VisitNEONScalarCopy()
6946 int rn_index = imm5 >> (tz + 1); in VisitNEONScalarCopy()
Ddisasm-aarch64.cc10221 unsigned imm5 = instr->GetImmNEON5(); in SubstituteImmediateField() local
10223 int tz = CountTrailingZeros(imm5, 32); in SubstituteImmediateField()
10225 rd_index = imm5 >> (tz + 1); in SubstituteImmediateField()
/external/llvm-project/llvm/lib/Target/AArch64/
DSVEInstrFormats.td4323 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
4324 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
4330 bits<5> imm5;
4334 let Inst{20-16} = imm5;
4686 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
4687 asm, "\t$Zd, $imm5, $imm5b",
4690 bits<5> imm5;
4697 let Inst{9-5} = imm5;
4707 def : Pat<(nxv16i8 (op simm5_8b:$imm5, simm5_8b:$imm5b)),
4708 (!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dconstants-i64.ll232 define i64 @imm5() #0 {
233 ; CHECK-LABEL: imm5:
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
237 bits<5> imm5;
244 let Inst{4-0} = imm5;
DMips64InstrInfo.td926 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
932 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
938 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
237 bits<5> imm5;
244 let Inst{4-0} = imm5;
DMips64InstrInfo.td926 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
932 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
938 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td3831 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
3832 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
3838 bits<5> imm5;
3842 let Inst{20-16} = imm5;
4251 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
4252 asm, "\t$Zd, $imm5, $imm5b",
4255 bits<5> imm5;
4262 let Inst{9-5} = imm5;
4275 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
4276 asm, "\t$Zd, $imm5, $Rm",
[all …]
/external/llvm-project/lldb/source/Plugins/Instruction/MIPS/
DEmulateInstructionMIPS.cpp1502 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_SWSP() local
1523 address = address + imm5; in Emulate_SWSP()
1646 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_LWSP() local
1660 base_address = base_address + imm5; in Emulate_LWSP()
1752 int32_t imm5 = insn.getOperand(0).getImm(); in Emulate_JRADDIUSP() local
1771 int32_t result = src_opd_val + imm5; in Emulate_JRADDIUSP()
1782 context.SetRegisterPlusOffset(reg_info_sp, imm5); in Emulate_JRADDIUSP()
/external/skia/src/core/
DSkVM.cpp2175 void Assembler::sli4s(V d, V n, int imm5) { in sli4s() argument
2176 this->op(0b0'1'1'011110'0100'000'01010'1, n, d, ( imm5 & 5_mask)<<16); in sli4s()
2178 void Assembler::shl4s(V d, V n, int imm5) { in shl4s() argument
2179 this->op(0b0'1'0'011110'0100'000'01010'1, n, d, ( imm5 & 5_mask)<<16); in shl4s()
2181 void Assembler::sshr4s(V d, V n, int imm5) { in sshr4s() argument
2182 this->op(0b0'1'0'011110'0100'000'00'0'0'0'1, n, d, (-imm5 & 5_mask)<<16); in sshr4s()
2184 void Assembler::ushr4s(V d, V n, int imm5) { in ushr4s() argument
2185 this->op(0b0'1'1'011110'0100'000'00'0'0'0'1, n, d, (-imm5 & 5_mask)<<16); in ushr4s()
2297 int imm5 = (lane << 3) | 0b100; in movs() local
2298 this->op(0b0'0'0'01110000'00000'0'01'1'1'1, src, dst, (imm5 & 5_mask) << 16); in movs()
[all …]
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp3761 uint32_t imm5; // encoding for the shift amount in EmulateShiftImm() local
3784 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3795 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3803 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3810 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3820 (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
5389 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister() local
5390 shift_n = DecodeImmShift(typ, imm5, shift_t); in EmulateSTRRegister()
6581 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister() local
6582 shift_n = DecodeImmShift(type, imm5, shift_t); in EmulateLDRRegister()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp335 IOffsetT imm5) { in encodeShiftRotateImm5() argument
337 assert(imm5 < (1 << kShiftImmBits)); in encodeShiftRotateImm5()
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm; in encodeShiftRotateImm5()

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