| /external/vixl/test/aarch32/config/ |
| D | cond-sp-sp-operand-imm7-t32.json | 28 // MNEMONIC{<c>}.N <Rd>, SP #<imm7>
32 "Add", // ADD{<c>}{<q>} {SP}, SP, #<imm7> ; T2
33 "Sub" // SUB{<c>}{<q>} {SP}, SP, #<imm7> ; T1
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 358 const uint32_t imm7 = bits(opcode, 6, 0); in ThumbImm7Scaled() local
359 return imm7 * 4; in ThumbImm7Scaled()
|
| /external/llvm-project/lld/ELF/Arch/ |
| D | RISCV.cpp | 296 uint16_t imm7 = extractBits(val, 7, 7) << 6; in relocate() local
299 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | constants-i64.ll | 253 define i64 @imm7() #0 {
254 ; CHECK-LABEL: imm7:
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 644 unsigned imm7 = 0; in DecodeTRAP() local
646 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
657 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 636 unsigned imm7 = 0; in DecodeTRAP() local
638 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
649 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
|
| /external/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 636 unsigned imm7 = 0; in DecodeTRAP() local
638 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
649 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
|
| /external/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| D | EmulateInstructionARM64.cpp | 707 uint32_t imm7 = Bits32(opcode, 21, 15); in EmulateLDPSTP() local
775 idx = LSL(llvm::SignExtend64<7>(imm7), scale); in EmulateLDPSTP()
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2163 void hint(int imm7);
3846 unsigned imm7);
3858 unsigned imm7);
3882 unsigned imm7);
3894 unsigned imm7);
6137 static Instr ImmLSPair(int64_t imm7, unsigned access_size_in_bytes_log2) { in ImmLSPair() argument
6138 VIXL_ASSERT(IsMultiple(imm7, 1 << access_size_in_bytes_log2)); in ImmLSPair()
6139 int64_t scaled_imm7 = imm7 / (1 << access_size_in_bytes_log2); in ImmLSPair()
6183 static Instr ImmHint(int imm7) { in ImmHint() argument
6184 VIXL_ASSERT(IsUint7(imm7)); in ImmHint()
[all …]
|
| D | assembler-sve-aarch64.cc | 2887 unsigned imm7) { in cmphi() argument
2896 CompareVectors(pd, pg, zn, imm7, CMPHI_p_p_zi); in cmphi()
2902 unsigned imm7) { in cmphs() argument
2911 CompareVectors(pd, pg, zn, imm7, CMPHS_p_p_zi); in cmphs()
2917 unsigned imm7) { in cmplo() argument
2926 CompareVectors(pd, pg, zn, imm7, CMPLO_p_p_zi); in cmplo()
2932 unsigned imm7) { in cmpls() argument
2941 CompareVectors(pd, pg, zn, imm7, CMPLS_p_p_zi); in cmpls()
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| D | assembler-aarch64.cc | 1936 void Assembler::hint(int imm7) { in hint() argument
1937 VIXL_ASSERT(IsUint7(imm7)); in hint()
1938 Emit(HINT | ImmHint(imm7) | Rt(xzr)); in hint()
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| D | macro-assembler-aarch64.h | 1679 void Hint(int imm7) { in Hint() argument
1682 hint(imm7); in Hint()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 389 // ADD sp, sp, #<imm7>
399 // SUB sp, sp, #<imm7>
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 418 // ADD sp, sp, #<imm7>
428 // SUB sp, sp, #<imm7>
|
| D | ARMInstrMVE.td | 156 // taddrmode_imm7 := reg[r0-r7] +/- (imm7 << shift)
174 // t2addrmode_imm7 := reg +/- (imm7)
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| D | ARMInstrThumb2.td | 295 // t2addrmode_imm7s4 := reg +/- (imm7 << 2)
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 422 // ADD sp, sp, #<imm7>
432 // SUB sp, sp, #<imm7>
|
| D | ARMInstrMVE.td | 118 // taddrmode_imm7 := reg[r0-r7] +/- (imm7 << shift)
136 // t2addrmode_imm7 := reg +/- (imm7)
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| D | ARMInstrThumb2.td | 296 // t2addrmode_imm7s4 := reg +/- (imm7 << 2)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 3925 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
3926 asm, "\t$Pd, $Pg/z, $Zn, $imm7",
3932 bits<7> imm7;
3936 let Inst{20-14} = imm7;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 4385 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
4386 asm, "\t$Pd, $Pg/z, $Zn, $imm7",
4392 bits<7> imm7;
4396 let Inst{20-14} = imm7;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 839 void hint(int imm7)
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 5807 // op: imm7
|