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Searched refs:imm8 (Results 1 – 25 of 100) sorted by relevance

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/external/elfutils/libcpu/defs/
Di3868 %mask {imm8} 8
104 00001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m}
106 00001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m}
108 00001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m}
110 00001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m}
137 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
138 11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
139 01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg}
140 00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
142 `11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg}
[all …]
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-operand-immediate-t32.json30 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8>
35 // ADD<c>{<q>} <Rdn>, #<imm8> ; T2
36 // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
38 // ADDS{<q>} <Rdn>, #<imm8> ; T2
39 // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
43 // SUB<c>{<q>} <Rdn>, #<imm8> ; T2
44 // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
46 // SUBS{<q>} <Rdn>, #<imm8> ; T2
47 // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
136 "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
[all …]
Dcond-rdlow-operand-imm8-t32.json28 // MNEMONIC{<c>}.N <Rdn>, #<imm8>
32 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
33 "Mov", // MOV<c>{<q>} <Rd>, #<imm8> ; T1
34 "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
85 "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1
86 "Mov" // MOV<c>{<q>} <Rd>, #<imm8> ; T1
Dcond-rd-pc-operand-imm8-t32.json28 // MNEMONIC{<c>}.W <Rd>, PC, #<imm8> ; wide encoding
32 "Add" // ADD{<c>}{<q>} <Rd>, PC, #<imm8> ; T1
Dcond-rd-sp-operand-imm8-t32.json28 // MNEMONIC{<c>}.N <rd>, SP #<imm8>
32 "Add" // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Dsimd16intrin.h50 #define _simd16_extract_ps(a, imm8) SIMD16::extract_ps<imm8>(a) argument
51 #define _simd16_extract_si(a, imm8) SIMD16::extract_si<imm8>(a) argument
52 #define _simd16_insert_ps(a, b, imm8) SIMD16::insert_ps<imm8>(a, b) argument
53 #define _simd16_insert_si(a, b, imm8) SIMD16::insert_si<imm8>(a, b) argument
151 #define _simd16_shuffle_epi32(a, b, imm8) SIMD16::shuffle_epi32<imm8>(a, b) argument
152 #define _simd16_shuffle_epi64(a, b, imm8) SIMD16::shuffle_epi64<imm8>(a, b) argument
Dsimdintrin.h163 #define _simd_shuffle_epi32(a, b, imm8) SIMD::shuffle_epi32<imm8>(a, b) argument
164 #define _simd_shuffle_epi64(a, b, imm8) SIMD::shuffle_epi64<imm8>(a, b) argument
/external/pffft/simd/
Dpf_neon_double_from_avx.h109 FORCE_INLINE __m128d _mm256_extractf128_pd (__m256d a, const int imm8) in _mm256_extractf128_pd() argument
111 assert(imm8 >= 0 && imm8 <= 1); in _mm256_extractf128_pd()
112 return a.vect_f64[imm8]; in _mm256_extractf128_pd()
Dpf_sse2_double.h157 FORCE_INLINE __m128d mm256_extractf128_pd (m256d a, const int imm8) in mm256_extractf128_pd() argument
159 assert(imm8 >= 0 && imm8 <= 1); in mm256_extractf128_pd()
160 return a.d128[imm8]; in mm256_extractf128_pd()
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc629 uint32_t imm8 = imm >> (24 - shift); in ImmediateT32() local
631 if ((imm8 <= 0xff) && ((imm8 & 0x80) != 0) && (overflow == 0)) { in ImmediateT32()
632 SetEncodingValue(((shift + 8) << 7) | (imm8 & 0x7F)); in ImmediateT32()
686 uint32_t imm8 = (imm << rot) | (imm >> (32 - rot)); in ImmediateA32() local
687 if (imm8 <= 0xff) { in ImmediateA32()
688 SetEncodingValue((rot << 7) | imm8); in ImmediateA32()
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DARMUtils.h351 const uint32_t imm8 = bits(opcode, 7, 0); in ThumbImm12() local
352 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12()
364 const uint32_t imm8 = bits(opcode, 7, 0); in ThumbImm8Scaled() local
365 return imm8 * 4; in ThumbImm8Scaled()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td168 // t_addrmode_pc := <label> => pc + imm8 * 4
271 // t_addrmode_sp := sp + imm8 * 4
395 // ADD <Rd>, sp, #<imm8>
940 bits<8> imm8;
942 let Inst{7-0} = imm8;
966 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
967 "add", "\t$Rdn, $imm8",
968 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
1000 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1003 imm8_255:$imm8))]>,
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/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td172 // t_addrmode_pc := <label> => pc + imm8 * 4
275 // t_addrmode_sp := sp + imm8 * 4
399 // ADD <Rd>, sp, #<imm8>
952 bits<8> imm8;
954 let Inst{7-0} = imm8;
978 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
979 "add", "\t$Rdn, $imm8",
980 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
1012 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1015 imm8_255:$imm8))]>,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td160 // t_addrmode_pc := <label> => pc + imm8 * 4
250 // t_addrmode_sp := sp + imm8 * 4
366 // ADD <Rd>, sp, #<imm8>
902 bits<8> imm8;
904 let Inst{7-0} = imm8;
927 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
928 "add", "\t$Rdn, $imm8",
929 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
1006 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1007 "cmp", "\t$Rn, $imm8",
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/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc75 int imm8; in TrySingleAddSub() local
77 if (imm.TryEncodeAsShiftedUintNForLane<8, 0>(zd, &imm8, &shift) || in TrySingleAddSub()
78 imm.TryEncodeAsShiftedUintNForLane<8, 8>(zd, &imm8, &shift)) { in TrySingleAddSub()
82 add(zd, zd, imm8, shift); in TrySingleAddSub()
85 sub(zd, zd, imm8, shift); in TrySingleAddSub()
368 int imm8; in Cpy() local
370 if (imm.TryEncodeAsShiftedIntNForLane<8, 0>(zd, &imm8, &shift) || in Cpy()
371 imm.TryEncodeAsShiftedIntNForLane<8, 8>(zd, &imm8, &shift)) { in Cpy()
373 cpy(zd, pg, imm8, shift); in Cpy()
482 int imm8; in Dup() local
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Dassembler-sve-aarch64.cc32 void Assembler::ResolveSVEImm8Shift(int* imm8, int* shift) { in ResolveSVEImm8Shift() argument
36 if (IsInt8(*imm8)) { in ResolveSVEImm8Shift()
38 } else if ((*imm8 % 256) == 0) { in ResolveSVEImm8Shift()
39 *imm8 /= 256; in ResolveSVEImm8Shift()
44 VIXL_ASSERT(IsInt8(*imm8)); in ResolveSVEImm8Shift()
3540 int imm8, in cpy() argument
3549 ResolveSVEImm8Shift(&imm8, &shift); in cpy()
3554 ImmField<12, 5>(imm8)); in cpy()
3574 int imm8, in SVEIntAddSubtractImmUnpredicatedHelper() argument
3579 if (IsUint8(imm8)) { in SVEIntAddSubtractImmUnpredicatedHelper()
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Dinstructions-aarch64.cc774 Float16 Instruction::Imm8ToFloat16(uint32_t imm8) { in Imm8ToFloat16() argument
778 uint32_t bits = imm8; in Imm8ToFloat16()
787 float Instruction::Imm8ToFP32(uint32_t imm8) { in Imm8ToFP32() argument
791 uint32_t bits = imm8; in Imm8ToFP32()
807 double Instruction::Imm8ToFP64(uint32_t imm8) { in Imm8ToFP64() argument
812 uint32_t bits = imm8; in Imm8ToFP64()
/external/llvm-project/llvm/test/TableGen/
DTargetInstrInfo.td18 def imm8 : RTLNode;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td18 def imm8 : RTLNode;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
123 bits<8> imm8;
128 let Inst{7-0} = imm8;
315 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
323 bits<8> imm8;
329 let Inst{7-0} = imm8;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td114 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
122 bits<8> imm8;
127 let Inst{7-0} = imm8;
314 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
322 bits<8> imm8;
328 let Inst{7-0} = imm8;
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrFormats.td114 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
122 bits<8> imm8;
127 let Inst{7-0} = imm8;
314 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
322 bits<8> imm8;
328 let Inst{7-0} = imm8;
/external/llvm/test/CodeGen/X86/
Dcommuted-blend-mask.ll4 ; mask can be encoded as a imm8.
/external/llvm-project/llvm/test/CodeGen/X86/
Dcommuted-blend-mask.ll5 ; mask can be encoded as a imm8.
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dbuilder_misc.h202 Value* VEXTRACTI128(Value* a, Constant* imm8);
203 Value* VINSERTI128(Value* a, Value* b, Constant* imm8);

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