| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-addrmode.ll | 6 ; base + offset (imm9)
16 ; base + offset (> imm9)
27 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-addrmode.ll | 6 ; base + offset (imm9)
16 ; base + offset (> imm9)
28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | constants-i64.ll | 275 define i64 @imm9() #0 {
276 ; CHECK-LABEL: imm9:
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 4968 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
4969 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
4974 bits<9> imm9;
4976 let Inst{21-16} = imm9{8-3};
4978 let Inst{12-10} = imm9{2-0};
4993 : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
4994 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
4999 bits<9> imm9;
5001 let Inst{21-16} = imm9{8-3};
5003 let Inst{12-10} = imm9{2-0};
[all …]
|
| /external/llvm-project/lldb/source/Plugins/Instruction/MIPS/ |
| D | EmulateInstructionMIPS.cpp | 1443 const uint32_t imm9 = insn.getOperand(0).getImm(); in Emulate_ADDIUSP() local
1453 result = src_opd_val + imm9; in Emulate_ADDIUSP()
1458 context.SetRegisterPlusOffset(reg_info_sp, imm9); in Emulate_ADDIUSP()
|
| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 4214 int64_t imm9 = addr.GetImmediateOffset(); in ldr() local
4215 VIXL_ASSERT(IsInt9(imm9)); in ldr()
4216 Instr imm9l = ExtractUnsignedBitfield32(2, 0, imm9) << 10; in ldr()
4217 Instr imm9h = ExtractUnsignedBitfield32(8, 3, imm9) << 16; in ldr()
5214 int64_t imm9 = addr.GetImmediateOffset(); in str() local
5215 VIXL_ASSERT(IsInt9(imm9)); in str()
5216 Instr imm9l = ExtractUnsignedBitfield32(2, 0, imm9) << 10; in str()
5217 Instr imm9h = ExtractUnsignedBitfield32(8, 3, imm9) << 16; in str()
|
| D | simulator-aarch64.cc | 9735 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10); in VisitSVELoadPredicateRegister() local
9736 uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9); in VisitSVELoadPredicateRegister()
9755 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10); in VisitSVELoadVectorRegister() local
9756 uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9); in VisitSVELoadVectorRegister()
10690 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10); in VisitSVEStorePredicateRegister() local
10691 uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9); in VisitSVEStorePredicateRegister()
10710 int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10); in VisitSVEStoreVectorRegister() local
10711 uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9); in VisitSVEStoreVectorRegister()
|
| D | assembler-aarch64.h | 6132 static Instr ImmLS(int64_t imm9) { in ImmLS() argument
6133 VIXL_ASSERT(IsInt9(imm9)); in ImmLS()
6134 return TruncateToUint9(imm9) << ImmLS_offset; in ImmLS()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 5534 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
5535 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
5540 bits<9> imm9;
5542 let Inst{21-16} = imm9{8-3};
5544 let Inst{12-10} = imm9{2-0};
5559 : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
5560 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
5565 bits<9> imm9;
5567 let Inst{21-16} = imm9{8-3};
5569 let Inst{12-10} = imm9{2-0};
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 7692 // op: imm9
11485 // op: imm9
|