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Searched refs:imm_type (Results 1 – 20 of 20) sorted by relevance

/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_asm.h86 unsigned imm_type : 2; member
145 .imm_type = type in etna_immediate_src()
Detnaviv_disasm.c371 switch (src->imm_type) { in print_src()
/external/mesa3d/src/intel/compiler/
Dbrw_reg_type.c93 enum hw_imm_type imm_type; member
317 assert(table[type].imm_type != (enum hw_imm_type)INVALID); in brw_reg_type_to_hw_type()
318 return table[type].imm_type; in brw_reg_type_to_hw_type()
352 if (table[i].imm_type == (enum hw_imm_type)hw_type) { in brw_hw_type_to_reg_type()
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td905 SDPatternOperator imm_type, ValueType Opg> {
913 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
914 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
915 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
916 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
917 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
918 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
DMips16InstrInfo.td1320 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1321 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1322 (I CPU16Regs:$in, imm_type:$imm)>;
1393 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1394 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1395 (I CPU16Regs:$rx, imm_type:$imm16)>;
DMipsInstrInfo.td1110 SDPatternOperator imm_type = null_frag,
1114 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1281 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1285 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td144 multiclass pseudo_binary_v_vv_vx_vi<Operand imm_type = simm5,
154 defm _VI : pseudo_binary<evr, evr, imm_type, m>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td1055 SDPatternOperator imm_type, ValueType Opg> {
1063 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1064 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1065 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1066 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1067 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1068 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
DMips16InstrInfo.td1323 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1325 (I CPU16Regs:$in, imm_type:$imm)>;
1396 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1397 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1398 (I CPU16Regs:$rx, imm_type:$imm16)>;
DMipsInstrInfo.td1327 SDPatternOperator imm_type = null_frag,
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1522 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1526 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td1055 SDPatternOperator imm_type, ValueType Opg> {
1063 def : MipsPat<(select (Opg (seteq RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1064 (OROp (SELEQZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1065 (SELNEZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
1066 def : MipsPat<(select (Opg (setne RC:$cond, imm_type:$imm)), RC:$t, RC:$f),
1067 (OROp (SELNEZOp RC:$t, (XORiOp RC:$cond, imm_type:$imm)),
1068 (SELEQZOp RC:$f, (XORiOp RC:$cond, imm_type:$imm)))>;
DMips16InstrInfo.td1323 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1325 (I CPU16Regs:$in, imm_type:$imm)>;
1396 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1397 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1398 (I CPU16Regs:$rx, imm_type:$imm16)>;
DMipsInstrInfo.td1327 SDPatternOperator imm_type = null_frag,
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1522 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
1526 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
/external/mesa3d/src/intel/tools/
Di965_gram.y514 %type <reg_type> reg_type imm_type
1591 immval imm_type
2104 imm_type:
/external/pcre/dist2/src/sljit/
DsljitNativeS390X.c505 #define SLJIT_S390X_RIA(name, pattern, imm_type) \ argument
506 SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, imm_type imm) \
542 #define SLJIT_S390X_RILA(name, pattern, imm_type) \ argument
543 SLJIT_S390X_INSTRUCTION(name, sljit_gpr reg, imm_type imm) \
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1923 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1925 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1965 RegisterClass regtype, Operand imm_type, string asm>
1966 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1998 RegisterClass regtype, Operand imm_type, string asm>
1999 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2000 imm_type:$imms),
2036 RegisterClass sregtype, Operand imm_type, string asm,
2038 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
6708 Operand imm_type, string asm,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td2499 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
2501 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
2541 RegisterClass regtype, Operand imm_type, string asm>
2542 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
2574 RegisterClass regtype, Operand imm_type, string asm>
2575 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2576 imm_type:$imms),
2612 RegisterClass sregtype, Operand imm_type, string asm,
2614 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
7575 Operand imm_type, string asm,
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td2635 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
2637 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
2677 RegisterClass regtype, Operand imm_type, string asm>
2678 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
2710 RegisterClass regtype, Operand imm_type, string asm>
2711 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2712 imm_type:$imms),
2748 RegisterClass sregtype, Operand imm_type, string asm,
2750 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
7752 Operand imm_type, string asm,
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td1710 MVEVectorVTInfo VTI, Operand imm_type, SDNode op> {
1712 (ins MQPR:$Qd_src, imm_type:$imm)> {
1722 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>;
1725 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm,
1730 multiclass MVE_VORRimm<MVEVectorVTInfo VTI, Operand imm_type> {
1731 defm "": MVE_bit_cmode_p<"vorr", 0, VTI, imm_type, ARMvorrImm>;
1733 multiclass MVE_VBICimm<MVEVectorVTInfo VTI, Operand imm_type> {
1734 defm "": MVE_bit_cmode_p<"vbic", 1, VTI, imm_type, ARMvbicImm>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td1405 class MVE_VORR<string suffix, bits<4> cmode, ExpandImm imm_type>
1406 : MVE_bit_cmode<"vorr", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {
1434 class MVE_VBIC<string suffix, bits<4> cmode, ExpandImm imm_type>
1435 : MVE_bit_cmode<"vbic", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {