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Searched refs:in7 (Results 1 – 25 of 40) sorted by relevance

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/external/libvpx/libvpx/vp9/encoder/mips/msa/
Dvp9_fdct8x8_msa.c19 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vp9_fht8x8_msa() local
21 LD_SH8(input, stride, in0, in1, in2, in3, in4, in5, in6, in7); in vp9_fht8x8_msa()
23 SLLI_4V(in4, in5, in6, in7, 2); in vp9_fht8x8_msa()
27 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
28 in5, in6, in7); in vp9_fht8x8_msa()
29 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_fht8x8_msa()
30 in3, in4, in5, in6, in7); in vp9_fht8x8_msa()
31 VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
32 in5, in6, in7); in vp9_fht8x8_msa()
35 VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in4, in vp9_fht8x8_msa()
[all …]
Dvp9_fdct_msa.h18 #define VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \ argument
35 ILVRL_H2_SH(in0, in7, vec1_m, vec0_m); \
38 cnst2_m, cnst3_m, in7, in0, in4, in3); \
52 BUTTERFLY_4(in7, in0, in2, in5, s1_m, s0_m, in2, in5); \
Dvp9_fdct16x16_msa.c369 v8i16 in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11; in postproc_fdct16x8_1d_row() local
372 LD_SH8(temp, 16, in0, in1, in2, in3, in4, in5, in6, in7); in postproc_fdct16x8_1d_row()
375 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in postproc_fdct16x8_1d_row()
376 in4, in5, in6, in7); in postproc_fdct16x8_1d_row()
382 FDCT_POSTPROC_2V_NEG_H(in6, in7); in postproc_fdct16x8_1d_row()
387 BUTTERFLY_16(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in postproc_fdct16x8_1d_row()
397 in4, in5, in6, in7); in postproc_fdct16x8_1d_row()
401 TRANSPOSE8x8_SH_SH(tmp4, in4, tmp5, in5, tmp6, in6, tmp7, in7, tmp4, in4, in postproc_fdct16x8_1d_row()
402 tmp5, in5, tmp6, in6, tmp7, in7); in postproc_fdct16x8_1d_row()
404 ST_SH8(tmp4, in4, tmp5, in5, tmp6, in6, tmp7, in7, out, 16); in postproc_fdct16x8_1d_row()
/external/libvpx/libvpx/vp9/common/mips/msa/
Dvp9_idct8x8_msa.c19 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vp9_iht8x8_64_add_msa() local
22 LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
24 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
25 in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
30 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
31 in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
33 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in vp9_iht8x8_64_add_msa()
34 in3, in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
35 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vp9_iht8x8_64_add_msa()
36 in4, in5, in6, in7); in vp9_iht8x8_64_add_msa()
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Didct8x8_msa.c16 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vpx_idct8x8_64_add_msa() local
19 LD_SH8(input, 8, in0, in1, in2, in3, in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
22 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
23 in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
25 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
26 in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
28 TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
29 in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
31 VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3, in vpx_idct8x8_64_add_msa()
32 in4, in5, in6, in7); in vpx_idct8x8_64_add_msa()
[all …]
Dfwd_txfm_msa.c15 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in vpx_fdct8x8_1_msa() local
18 LD_SH8(input, stride, in0, in1, in2, in3, in4, in5, in6, in7); in vpx_fdct8x8_1_msa()
19 ADD4(in0, in1, in2, in3, in4, in5, in6, in7, in0, in2, in4, in6); in vpx_fdct8x8_1_msa()
31 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in fdct8x16_1d_column() local
44 LD_SH16(input, src_stride, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in fdct8x16_1d_column()
47 SLLI_4V(in4, in5, in6, in7, 2); in fdct8x16_1d_column()
51 ADD4(in4, in11, in5, in10, in6, in9, in7, in8, tmp4, tmp5, tmp6, tmp7); in fdct8x16_1d_column()
56 SUB4(in4, in11, in5, in10, in6, in9, in7, in8, in11, in10, in9, in8); in fdct8x16_1d_column()
150 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in fdct16x8_1d_row() local
153 LD_SH8(input, 16, in0, in1, in2, in3, in4, in5, in6, in7); in fdct16x8_1d_row()
[all …]
Dmacros_msa.h331 #define ST_V8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
334 ST_V4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride); \
488 #define AVER_UB4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
492 AVER_UB2(RTYPE, in4, in5, in6, in7, out2, out3) \
1005 #define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1009 ILVL_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
1062 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1066 ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
1073 #define ILVR_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, \ argument
1077 ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \
[all …]
Dfwd_dct32x32_msa.c17 v8i16 in0, in1, in2, in3, in4, in5, in6, in7; in fdct8x32_1d_column_load_butterfly() local
24 LD_SH4(input + (28 * src_stride), src_stride, in4, in5, in6, in7); in fdct8x32_1d_column_load_butterfly()
28 SLLI_4V(in4, in5, in6, in7, 2); in fdct8x32_1d_column_load_butterfly()
31 BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7, step0, step1, step2, in fdct8x32_1d_column_load_butterfly()
32 step3, in4, in5, in6, in7); in fdct8x32_1d_column_load_butterfly()
36 ST_SH4(in4, in5, in6, in7, temp_buff + (28 * 8), 8); in fdct8x32_1d_column_load_butterfly()
42 LD_SH4(input + (20 * src_stride), src_stride, in4, in5, in6, in7); in fdct8x32_1d_column_load_butterfly()
46 SLLI_4V(in4, in5, in6, in7, 2); in fdct8x32_1d_column_load_butterfly()
49 BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7, step0, step1, step2, in fdct8x32_1d_column_load_butterfly()
50 step3, in4, in5, in6, in7); in fdct8x32_1d_column_load_butterfly()
[all …]
Dinv_txfm_msa.h18 #define VP9_ADST8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \ argument
35 ILVRL_H2_SH(in0, in7, vec1_m, vec0_m); \
38 cnst2_m, cnst3_m, in7, in0, in4, in3); \
52 BUTTERFLY_4(in7, in0, in2, in5, s1_m, s0_m, in2, in5); \
214 #define VP9_IDCT8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
227 VP9_MADD(in1, in7, in3, in5, k0_m, k1_m, k2_m, k3_m, in1, in7, in3, in5); \
228 SUB2(in1, in3, in7, in5, res0_m, res1_m); \
238 tp7_m = in7 + in5; \
247 #define VP9_IADST8x8_1D(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
286 ILVRL_H2_SH(in7, in6, in_s1, in_s0); \
[all …]
Dfwd_txfm_msa.h46 #define SRLI_AVE_S_4V_H(in0, in1, in2, in3, in4, in5, in6, in7) \ argument
51 SRLI_H4_SH(in4, in5, in6, in7, vec4_m, vec5_m, vec6_m, vec7_m, 15); \
54 AVE_SH4_SH(vec4_m, in4, vec5_m, in5, vec6_m, in6, vec7_m, in7, in4, in5, \
55 in6, in7); \
58 #define VP9_FDCT8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \ argument
67 BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7, s0_m, s1_m, s2_m, \
118 #define FDCT8x16_EVEN(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
127 BUTTERFLY_8(in0, in1, in2, in3, in4, in5, in6, in7, s0_m, s1_m, s2_m, \
Dtxfm_macros_msa.h40 #define DOT_ADD_SUB_SRARI_PCK(in0, in1, in2, in3, in4, in5, in6, in7, dst0, \ argument
48 DOTP_SH4_SW(in2, in3, in2, in3, in6, in6, in7, in7, tp5_m, tp6_m, tp7_m, \
Ddeblock_msa.c19 in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3, out4, \ argument
25 ILVR_B4_SH(in1, in0, in3, in2, in5, in4, in7, in6, temp0, temp1, temp2, \
31 ILVL_B4_SH(in1, in0, in3, in2, in5, in4, in7, in6, temp0, temp1, temp2, \
74 #define TRANSPOSE12x16_B(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, \ argument
82 ILVR_B2_SH(in5, in4, in7, in6, temp0, temp1); \
97 ILVL_B2_SH(in5, in4, in7, in6, temp0, temp1); \
100 in7 = (v16u8)__msa_ilvl_d((v2i64)temp7, (v2i64)temp3); \
113 #define VPX_TRANSPOSE12x8_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, in8, \ argument
121 ILVR_B2_SH(in5, in4, in7, in6, temp0, temp1); \
127 ILVL_B2_SH(in5, in4, in7, in6, temp6, temp7); \
[all …]
/external/tensorflow/tensorflow/core/kernels/
Daggregate_ops_gpu.cu.cc97 typename TTypes<T>::ConstFlat in7) { in operator ()()
99 in7); in operator ()()
110 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) { in operator ()()
112 in7, in8); in operator ()()
123 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) { in operator ()()
125 in7, in8); in operator ()()
136 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8, in operator ()()
139 in7, in8, in9); in operator ()()
Daggregate_ops_cpu.h91 typename TTypes<T>::ConstFlat in7) {
93 in7);
104 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) {
106 in7, in8);
117 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) {
119 in7, in8);
130 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8,
133 in7, in8, in9);
Daggregate_ops.h137 typename TTypes<T>::ConstFlat in7);
149 typename TTypes<T>::ConstFlat in7) { in Compute()
150 out.device(d) = in1 + in2 + in3 + in4 + in5 + in6 + in7; in Compute()
161 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8);
171 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) { in Compute()
172 out.device(d) = in1 + in2 + in3 + in4 + in5 + in6 + in7 + in8; in Compute()
185 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8);
195 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8) { in Compute()
196 out.device(d) += in1 + in2 + in3 + in4 + in5 + in6 + in7 + in8; in Compute()
207 typename TTypes<T>::ConstFlat in7, typename TTypes<T>::ConstFlat in8,
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/external/libaom/libaom/aom_dsp/mips/
Dmacros_msa.h423 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
426 ST_B4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride); \
449 #define ST_H8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
452 ST_H4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride); \
616 #define AVER_UB4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
620 AVER_UB2(RTYPE, in4, in5, in6, in7, out2, out3) \
1116 #define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1120 ILVL_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
1173 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1177 ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
[all …]
/external/libaom/libaom/aom_dsp/x86/
Dfwd_txfm_impl_sse2.h259 __m128i in7 = _mm_load_si128((const __m128i *)(input + 7 * stride)); in FDCT8x8_2D() local
268 in7 = _mm_slli_epi16(in7, 2); in FDCT8x8_2D()
278 const __m128i q0 = ADD_EPI16(in0, in7); in FDCT8x8_2D()
285 const __m128i q7 = SUB_EPI16(in0, in7); in FDCT8x8_2D()
491 in7 = _mm_unpackhi_epi64(tr1_3, tr1_7); in FDCT8x8_2D()
514 const __m128i sign_in7 = _mm_srai_epi16(in7, 15); in FDCT8x8_2D()
522 in7 = _mm_sub_epi16(in7, sign_in7); in FDCT8x8_2D()
530 in7 = _mm_srai_epi16(in7, 1); in FDCT8x8_2D()
539 store_output(&in7, (output + 7 * 8)); in FDCT8x8_2D()
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h360 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) \ argument
363 ST_B4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride); \
953 #define ILVL_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
957 ILVL_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
1008 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1012 ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
1035 #define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1039 ILVR_H2(RTYPE, in4, in5, in6, in7, out2, out3); \
1067 #define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, \ argument
1071 ILVR_D2(RTYPE, in4, in5, in6, in7, out2, out3); \
[all …]
/external/boringssl/src/crypto/fipsmodule/aes/asm/
Daesp8-ppc.pl674 my ($in0, $in1, $in2, $in3, $in4, $in5, $in6, $in7 )=map("v$_",(0..3,10..13));
791 lvx_u $in7,$x70,$inp
797 le?vperm $in7,$in7,$in7,$inpperm
800 vxor $out7,$in7,$rndkey0
929 vmr $ivec,$in7
931 lvx_u $in7,$x70,$inp
941 le?vperm $in7,$in7,$in7,$inpperm
960 vxor $out7,$in7,$rndkey0
1075 vmr $ivec,$in7
1102 vmr $ivec,$in7
[all …]
/external/webp/src/dsp/
Dmsa_macro.h310 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \ argument
313 ST_B4(RTYPE, in4, in5, in6, in7, pdst + 4 * stride, stride); \
873 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \ argument
876 ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
899 #define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \ argument
902 ILVR_H2(RTYPE, in4, in5, in6, in7, out2, out3); \
923 #define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \ argument
926 ILVR_D2(RTYPE, in4, in5, in6, in7, out2, out3); \
984 #define PCKEV_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \ argument
987 PCKEV_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
[all …]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dlong-chains.ll4 define i8 @longchain(i8 %in1, i8 %in2, i8 %in3, i8 %in4, i8 %in5, i8 %in6, i8 %in7, i8 %in8, i8 %in…
12 %tmp8 = add i8 %tmp7, %in7
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h284 __m128i in7 = _mm_load_si128((const __m128i *)(input + 7 * stride)); in FDCT8x8_2D() local
293 in7 = _mm_slli_epi16(in7, 2); in FDCT8x8_2D()
303 const __m128i q0 = ADD_EPI16(in0, in7); in FDCT8x8_2D()
310 const __m128i q7 = SUB_EPI16(in0, in7); in FDCT8x8_2D()
516 in7 = _mm_unpackhi_epi64(tr1_3, tr1_7); in FDCT8x8_2D()
539 const __m128i sign_in7 = _mm_srai_epi16(in7, 15); in FDCT8x8_2D()
547 in7 = _mm_sub_epi16(in7, sign_in7); in FDCT8x8_2D()
555 in7 = _mm_srai_epi16(in7, 1); in FDCT8x8_2D()
564 store_output(&in7, (output + 7 * 8)); in FDCT8x8_2D()
/external/libvpx/libvpx/vpx_dsp/ppc/
Dinv_txfm_vsx.c234 #define TRANSPOSE8x8(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, \ argument
242 out6 = vec_mergeh(in6, in7); \
243 out7 = vec_mergel(in6, in7); \
251 in7 = (int16x8_t)vec_mergel((int32x4_t)out5, (int32x4_t)out7); \
258 out6 = vec_perm(in3, in7, tr8_mask0); \
259 out7 = vec_perm(in3, in7, tr8_mask1);
293 #define IDCT8(in0, in1, in2, in3, in4, in5, in6, in7) \ argument
300 STEP8_0(in1, in7, step4, step7, cospi28_v, cospi4_v); \
309 in7 = vec_add(step6, step7); \
318 step7 = in7; \
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Damdhsa-trap-num-sgprs.ll15 i32 addrspace(1)* %out7, i32 %in7,
46 store i32 %in7, i32 addrspace(1)* %out7
/external/libvpx/libvpx/vpx_dsp/arm/
Dhighbd_idct32x32_135_add_neon.c23 int32x4x2_t *const in5, int32x4x2_t *const in6, int32x4x2_t *const in7) { in load_8x8_s32_dual() argument
45 in7->val[0] = vld1q_s32(input); in load_8x8_s32_dual()
46 in7->val[1] = vld1q_s32(input + 4); in load_8x8_s32_dual()
54 int32x4_t *const in7) { in load_4x8_s32_dual() argument
69 *in7 = vld1q_s32(input); in load_4x8_s32_dual()

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